专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080247233A1 NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件，非易失性存储器系统和非易失性存储器件的控制方法
公开(公告)号：US20080247233A1
公开(公告)日：2008-10-09
申请号：US12058471
申请日：2008-03-28
申请人： Shozo Kawabata , Sooyong Park
发明人： Shozo Kawabata , Sooyong Park
IPC分类号： G11C16/04 , G11C8/00 , G11C5/14
CPC分类号： G11C16/0491 , G11C16/26
摘要： A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device 1 comprises a booster controller circuit 10, a booster circuit 20, a level-shifting circuit 30, a Y-decoder 40, and a main circuit 50. A NAND gate ND1, a NOR gate NR1, and a NOR gate NR2 provided in the booster controller circuit 10 output kick signals KICK0 to KICK2. The booster circuit 20 comprises boosting systems B0, B1, B2 which respectively receive the kick signals KICK0, KICK1, and KICK2. The kick signals KICK0 and KICK1 outputted from the NAND gate ND1 and the NOR gate NR1 make transition to high level in accordance with the transition of column address coladd from address 7 to 8. Therefore, the boosting system B0 is activated in addition to the boosting system B1.
摘要翻译：提供一种能够降低消耗电流并缩短访问时间的非易失性存储装置及其控制方法。非易失性存储器件1包括升压控制器电路10，升压电路20，电平移位电路30，Y解码器40和主电路50。在升压控制电路10中设置的NAND门ND1，NOR门NR1，NOR门NR2输出启动信号KICK0〜KICK2。升压电路20包括分别接收启动信号KICK 0，KICK 1和KICK 2的升压系统B 0，B 1，B 2。从与非门ND 1和或非门NR 1输出的触发信号KICK 0和KICK 1根据从地址7到8的列地址的转换转换到高电平。因此，升压系统B 0除了升压系统B1之外也被激活。

2. 发明授权

US07859914B2 Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is varied 有权
标题翻译：用于非易失性存储器件的非易失性存储器件，非易失性存储器系统和控制方法，其中选择晶体管的驱动能力变化
公开(公告)号：US07859914B2
公开(公告)日：2010-12-28
申请号：US12058471
申请日：2008-03-28
申请人： Shozo Kawabata , Sooyong Park
发明人： Shozo Kawabata , Sooyong Park
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0491 , G11C16/26
摘要： The control method includes a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within a memory block.
摘要翻译：控制方法包括：当所选择的存储单元产生时，选择晶体管的选择晶体管的驱动能力的步骤，所述选择晶体管选择所选择的存储单元中的扩散层和至少一个与所选存储单元相邻的未选择的存储单元的扩散层从一端的存储单元转换到存储器块内另一端的存储单元。

3. 发明授权

US07433219B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US07433219B2
公开(公告)日：2008-10-07
申请号：US11341029
申请日：2006-01-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

4. 发明授权

US4882314A A composition and method of treating selected malignant conditions 失效
标题翻译：一种治疗所选恶性病症的组合物和方法
公开(公告)号：US4882314A
公开(公告)日：1989-11-21
申请号：US81480
申请日：1987-08-04
申请人： Setsuo Takeuchi , Mutsuyuki Kochi , Akira Kawarada , Shinichiro Esumi , Kaguya Sasaki , Shozo Kawabata , Tsuneo Saita , Yukio Inoue , Makoto Yamamoto , Keiji Sekine
发明人： Setsuo Takeuchi , Mutsuyuki Kochi , Akira Kawarada , Shinichiro Esumi , Kaguya Sasaki , Shozo Kawabata , Tsuneo Saita , Yukio Inoue , Makoto Yamamoto , Keiji Sekine
IPC分类号： A61K31/70
CPC分类号： A61K31/7004
摘要： Disclosed is a novel carcinostatic composition comprising 4,6-0-benzylidene-D-glucopyranose as the active ingredient. This active ingredient exerts a very high carcinostatic activity according to a specific carcinostatic mechanism quite different from that of conventional carcinostatic chemotherapeutic agents. The active ingredient is very low in toxicity and is highly stable and water-soluble. This composition is effective against selected malignant conditions which are carcinoma of the colon, cancer of the stomach, cancer of the tongue, peritonitis carcinomatosa, cancer of the liver and malignancies induced by SV.sub.40 virus.
摘要翻译：公开了一种包含4,6-0-亚苄基-D-吡喃葡萄糖作为活性成分的新型制癌组合物。该活性成分根据与传统制癌化学治疗剂完全不同的特定制癌机制，发挥非常高的制癌活性。活性成分毒性非常低，稳定性高，水溶性好。该组合物对于结肠癌，胃癌，舌癌，腹膜炎，肝癌，SV40病毒诱导的恶性肿瘤等恶性病症有效。

5. 发明授权

US08023341B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US08023341B2
公开(公告)日：2011-09-20
申请号：US12903065
申请日：2010-10-12
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C7/10
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

6. 发明授权

US07415568B2 Method and apparatus for initialization control in a non-volatile memory device 有权
标题翻译：用于非易失性存储器件中的初始化控制的方法和装置
公开(公告)号：US07415568B2
公开(公告)日：2008-08-19
申请号：US11194111
申请日：2005-07-28
申请人： Shozo Kawabata , Takaaki Furuyama , Kenta Kato
发明人： Shozo Kawabata , Takaaki Furuyama , Kenta Kato
IPC分类号： G11C16/02
CPC分类号： G11C7/1051 , G11C7/1063 , G11C7/20 , G11C16/20 , G11C16/26 , G11C16/344
摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.
摘要翻译：当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12））。在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据外部读取访问请求到非冗余存储器区域。在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。此后，读出重写操作信息（S18）。因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

7. 发明授权

US07120050B2 Method and apparatus for setting operational information of a non-volatile memory 有权
公开(公告)号：US07120050B2
公开(公告)日：2006-10-10
申请号：US11259873
申请日：2005-10-26
申请人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
发明人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C16/102 , G11C16/20 , G11C16/3436 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402
摘要： A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (25), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier (19) is stored in the volatile data retaining unit (25). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit (25) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

8. 发明申请

US20060098496A1 Method and apparatus for setting operational information of a non-volatile memory 有权
标题翻译：用于设置非易失性存储器的操作信息的方法和装置
公开(公告)号：US20060098496A1
公开(公告)日：2006-05-11
申请号：US11259873
申请日：2005-10-26
申请人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
发明人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
IPC分类号： G11C7/10
CPC分类号： G11C29/02 , G11C16/102 , G11C16/20 , G11C16/3436 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402
摘要： A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (25), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier (19) is stored in the volatile data retaining unit (25). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit (25) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.
摘要翻译：验证读出放大器（19）从要被重写的非易失性存储器单元读取数据。读出数据与比较器电路（21）中的期望数据进行比较。在完成重写时，比较器电路（21）输出匹配信号MCH。选择器（23）对应于要重写的非易失性存储器单元MC输出指示易失性数据保持单元（25）的解码信号STR（i）或SWP（i）。根据验证指示信号PGV / ERV，将由验证读出放大器（19）读出的读出数据存储在易失性数据保持单元（25）中。通过匹配信号MCH而不是验证指令信号PGV / ERV进行控制，从而在完成重写时将数据存储在易失性数据保持单元（25）中。因此，不需要从非易失性存储器重新读取操作信息。

9. 发明授权

US06862217B2 Control method of non-volatile semiconductor memory cell and non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器单元和非易失性半导体存储器件的控制方法
公开(公告)号：US06862217B2
公开(公告)日：2005-03-01
申请号：US10665205
申请日：2003-09-22
申请人： Shozo Kawabata
发明人： Shozo Kawabata
IPC分类号： G11C16/02 , G11C16/10 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/3459
摘要： It is intended to provide control method and a nonvolatile semiconductor memory device capable of erase operation or write operation in high speed securing reliability without applying excessive electric field. An operation unit consists of a plurality of operation cycles each of which has a bias-application period and a verification period. Addition voltage ΔV is added to each operation unit as bias voltage, whereby a write operation can be carried out with characteristic of injected current IFG that is uniform among respective operation units duration of which are generally same. In this case, duration of operation cycles are shortened by each operation unit and duration of verification periods are shortened so as to avoid a situation such that a write operation completes in the middle of a bias-application period and after that, another write operation continues to cause excessive voltage stress on non-volatile semiconductor memory cells.
摘要翻译：旨在提供控制方法和非易失性半导体存储器件，其能够在不施加过大电场的情况下以高速确保可靠性进行擦除操作或写入操作。操作单元由多个操作循环组成，每个操作循环具有偏置施加周期和验证周期。将加法电压DeltaV作为偏置电压加到每个操作单元上，由此可以以相同操作单元的持续时间大致相同的注入电流IFG的特性进行写入操作。在这种情况下，通过每个操作单元缩短操作周期的持续时间，并且缩短验证周期的持续时间，以避免在偏置施加期间的中间写入操作完成的情况，之后另一个写入操作继续以对非易失性半导体存储单元造成过大的电压应力。

10. 发明授权

US4153724A Benzoyl phenoxy acetic acid derivatives 失效
标题翻译：苯甲酰基苯氧基乙酸衍生物
公开(公告)号：US4153724A
公开(公告)日：1979-05-08
申请号：US860478
申请日：1977-12-14
申请人： Yasuhiko Hamazaki , Toshiyuki Yamamoto , Shozo Kawabata , Kenji Seri , Masao Sakasai , Reiko Sato , Nobuo Ishiyama
发明人： Yasuhiko Hamazaki , Toshiyuki Yamamoto , Shozo Kawabata , Kenji Seri , Masao Sakasai , Reiko Sato , Nobuo Ishiyama
IPC分类号： C07C59/90 , C07C69/95 , A61K31/19 , A61K31/215 , C07C65/20
CPC分类号： C07C59/90
摘要： Benzoyl phenoxy acetic acid derivatives having the formula ##STR1## wherein R.sub.1 represents hydrogen or halogen atom or a lower alkyl group or a lower alkoxyl group; and R.sub.2 represents hydrogen atom or a lower alkyl group which impart excellent antihyperlipidemic activity are provided.
摘要翻译：具有式“IMAGE”的苯甲酰基苯氧基乙酸衍生物，其中R 1表示氢或卤素原子或低级烷基或低级烷氧基; R2表示氢原子或提供优异的抗高脂血症活性的低级烷基。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式