专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6071812A Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes 有权
标题翻译：形成改性金属接触开口以降低其深亚微米工艺的纵横比的方法
公开(公告)号：US6071812A
公开(公告)日：2000-06-06
申请号：US174622
申请日：1998-10-19
申请人： Shou-Yi Hsu , Hon-Hung Lui , Kun-Jung Chuang
发明人： Shou-Yi Hsu , Hon-Hung Lui , Kun-Jung Chuang
IPC分类号： H01L21/311 , H01L21/768 , H01L23/485 , H01L21/44 , H01L21/31 , H01L21/469 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/31144 , H01L21/76804 , H01L2924/0002
摘要： A method of fabricating a metal contact in a reduced aspect ratio contact hole. The method begins by forming a first insulating layer and a first barrier layer having a first barrier opening over a substrate. The first insulating layer is anisotropically etched through the first barrier opening forming an upper contact hole. A second barrier layer is formed on the first barrier layer and the first insulating layer. The second barrier layer is anisotropically etched forming spacers on sidewalls of the first insulating layer. The first insulating layer is anisotropically etched using the first barrier layer and the spacers as an etch mask forming a lower contact hole. The first barrier layer and the spacers are removed to form the reduced aspect ratio contact hole. The reduced aspect ratio contact hole is comprised by the upper and lower contact holes. The reduced aspect ratio contact hole is filled with a contact metal to contact the contact region in the substrate.
摘要翻译：一种在缩小的纵横比接触孔中制造金属接触的方法。该方法开始于在衬底上形成第一绝缘层和具有第一阻挡开口的第一阻挡层。第一绝缘层通过形成上接触孔的第一阻挡开口被各向异性地蚀刻。在第一阻挡层和第一绝缘层上形成第二阻挡层。第二阻挡层被各向异性地蚀刻，在第一绝缘层的侧壁上形成间隔物。使用第一阻挡层和间隔物作为形成下接触孔的蚀刻掩模来各向异性地蚀刻第一绝缘层。去除第一阻挡层和间隔物以形成减小的纵横比接触孔。缩小的纵横比接触孔由上接触孔和下接触孔组成。缩小的纵横比接触孔填充有接触金属以接触基板中的接触区域。

2. 发明授权

US6153517A Low resistance poly landing pad 有权
标题翻译：低阻多层落地垫
公开(公告)号：US6153517A
公开(公告)日：2000-11-28
申请号：US266880
申请日：1999-03-12
申请人： Kun-Jung Chuang , Shou-Yi Hsu , Yi-Te Chen , Hon-Hung Lui
发明人： Kun-Jung Chuang , Shou-Yi Hsu , Yi-Te Chen , Hon-Hung Lui
IPC分类号： H01L21/768 , H01L23/485 , H01L21/44
CPC分类号： H01L21/76855 , H01L21/76843 , H01L21/76849 , H01L21/76889 , H01L23/485 , H01L2924/0002
摘要： A method is disclosed for forming a low resistance poly landing pad which is achieved by shunting the polysilicon of a landing pad with metallic conductors. A window is opened through a first dielectric layer to expose a conducting region over a semiconductor substrate. A metallic layer, deposited overall, is followed by an overall deposition of a polysilicon layer, with the layers being sufficient to fill the window completely. Metal and polysilicon outside the window is removed by chemical/mechanical polishing which also provides global planarization. Salicidation provides a silicide cover over the exposed surface of polysilicon, which was formed by the polishing. A second dielectric is deposited and an opening is formed to the landing pad. Electrical contact is made between metallization on the second dielectric layer and the salicide of the landing pad either, directly by simultaneous deposition of the metallization on the dielectric and the landing pad, or, by first forming a plug in the opening and then depositing the metallization.
摘要翻译：公开了一种用于形成低电阻多接地焊盘的方法，其通过用金属导体分流着陆焊盘的多晶硅来实现。通过第一电介质层打开窗口以暴露半导体衬底上的导电区域。整个沉积的金属层之后是多晶硅层的总体沉积，其中层足以完全填充窗口。通过化学/机械抛光除去窗户外的金属和多晶硅，还提供全局平面化。 Salicidation在多晶硅的暴露表面上提供硅化物覆盖层，其通过抛光形成。沉积第二电介质并且对着陆焊盘形成开口。在第二电介质层上的金属化和着陆焊盘的自对准硅化物之间进行电接触，直接通过金属化同时沉积在电介质和着陆焊盘上，或者首先在开口中形成插塞，然后沉积金属化。

3. 发明授权

US5869370A Ultra thin tunneling oxide using buffer CVD to improve edge thinning 失效
标题翻译：使用缓冲CVD氧化物的新型超薄隧穿氧化物，以改善边缘变薄效应
公开(公告)号：US5869370A
公开(公告)日：1999-02-09
申请号：US998631
申请日：1997-12-29
申请人： Kun-Jung Chuang , Hon-Hung Lui , Yi-Te Chen
发明人： Kun-Jung Chuang , Hon-Hung Lui , Yi-Te Chen
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/8247 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/66825
摘要： A new method of forming a tunneling oxide film having a uniform thickness in the fabrication of a Flash EEPROM memory cell is described. A first oxide layer is provided on the surface of a semiconductor substrate wherein a portion of the first oxide layer is removed to expose the semiconductor substrate wherein the exposed portion of the semiconductor substrate comprises a tunneling window. A second oxide layer is deposited within the tunneling window. Thereafter, a thermal oxide layer is grown underlying the first oxide layer and the second oxide layer within the tunneling area wherein the presence of the second oxide layer provides for a uniform thermal oxide thickness throughout the tunneling window and wherein the second oxide layer and the thermal oxide layer together within the tunneling window form the tunneling oxide film in the fabrication of a memory cell.
摘要翻译：描述了在制造闪存EEPROM存储单元中形成具有均匀厚度的隧道氧化物膜的新方法。第一氧化物层设置在半导体衬底的表面上，其中去除第一氧化物层的一部分以露出半导体衬底，其中半导体衬底的暴露部分包括隧道窗。第二氧化物层沉积在隧道窗内。此后，在隧道区域内的第一氧化物层和第二氧化物层下方生长热氧化物层，其中第二氧化物层的存在在整个隧道窗口中提供均匀的热氧化物厚度，并且其中第二氧化物层和热一起在隧道窗内的氧化物层在制造存储器单元中形成隧穿氧化膜。

4. 发明授权

US5879991A Trench free polysilicon gate definition process for a non-volatile memory device 失效
标题翻译：用于非易失性存储器件的无沟槽多晶硅栅极定义过程
公开(公告)号：US5879991A
公开(公告)日：1999-03-09
申请号：US984841
申请日：1997-12-04
申请人： Hon-Hung Lui , Shou-Yi Shiu
发明人： Hon-Hung Lui , Shou-Yi Shiu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method of creating a non-volatile memory device, featuring self-alignment of a control gate structure, to an underlying floating gate structure, has been developed. The formation of a first polysilicon floating gate shape, completely covering the semiconductor substrate, with openings only to underlying field oxide regions, prevents a deleterious trenching phenomena from occurring during a subsequent patterning, used to define an overlying, control gate structure. A photoresist shape is used as a mask to allow patterning of the control gate structure to be performed, via an anisotropic procedure, applied to a polysilicon layer, followed by the continuation of the anisotropic RIE procedure, applied to the first polysilicon floating gate shape, creating the floating gate structure.
摘要翻译：已经开发了一种创建具有控制栅极结构的自对准的非易失性存储器件到基础浮动栅极结构的方法。第一多晶硅浮栅形状，完全覆盖半导体衬底，仅具有开口到底层的场氧化物区域，防止在用于限定上覆控制栅结构的随后图案化期间发生有害的开沟现象。使用光致抗蚀剂形状作为掩模，以允许通过施加到多晶硅层的各向异性程序进行控制栅极结构的图案化，随后继续施加到第一多晶硅浮动栅极形状的各向异性RIE程序，创建浮动门结构。

5. 发明授权

US5956569A Integrated thermoelectric cooler formed on the backside of a substrate 失效
标题翻译：形成在基板背面的集成热电冷却器
公开(公告)号：US5956569A
公开(公告)日：1999-09-21
申请号：US957677
申请日：1997-10-24
申请人： Shou-Yi Shiu , Yu-Ping Fang , Hon-Hung Lui
发明人： Shou-Yi Shiu , Yu-Ping Fang , Hon-Hung Lui
IPC分类号： H01L23/38 , H01L21/00
CPC分类号： H01L23/38 , H01L2224/48091 , H01L2224/48137 , H01L2224/4823 , H01L24/48 , H01L2924/00014 , H01L2924/01019 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , Y10S136/293 , Y10S438/928
摘要： The present invention provides a structure and a method of fabricating a thermoelectric Cooler directly on the backside of a semiconductor substrate. The thermoelectric (TE) cooler (thermoelectric cooler) disperses heat from an integrated circuit (IC) that is formed on the front-side of the silicon substrate. Spaced first bonding pad holes 28 are formed in the backside of a substrate that expose bonding pads 24. Second holes 32 are formed between the spaced first bonding pad holes 28. A first insulating layer 34 is formed over the backside of the substrate, but not over the bonding pad 24. A metal layer is formed lining the first bonding pad holes 28. A polysilicon layer 46 is formed over the surface of the backside of the substrate in the second holes. The polysilicon layer is implanted thereby forming alternating adjacent N and P doped sections 46p 46n in the second holes. The adjacent N and P doped polysilicon sections 46n 46p are electrically connected to the bonding pads 24 by the metal layer 38.
摘要翻译：本发明提供了直接在半导体衬底的背面制造热电冷却器的结构和方法。热电（TE）冷却器（热电冷却器）从形成在硅衬底前侧的集成电路（IC）分散热量。间隔的第一焊盘孔28形成在暴露接合焊盘24的衬底的背面中。第二孔32形成在间隔开的第一接合焊盘孔28之间。第一绝缘层34形成在衬底的背面，但不是在接合焊盘24上形成金属层。在第一焊盘孔28内形成有金属层。多晶硅层46形成在第二孔中的衬底背面的表面上。注入多晶硅层，从而在第二孔中形成相邻的N和P掺杂部分46p 46n。相邻的N和P掺杂多晶硅部分46n 46p通过金属层38电连接到焊盘24。

6. 发明授权

US5956566A Method and test site to monitor alignment shift and buried contact trench formation 有权
标题翻译：方法和测试场地，用于监测对准位移和掩埋接触沟形成
公开(公告)号：US5956566A
公开(公告)日：1999-09-21
申请号：US213454
申请日：1998-12-17
申请人： Jyh-Feng Lin , Hon-Hung Lui , Yi-Te Chen
发明人： Jyh-Feng Lin , Hon-Hung Lui , Yi-Te Chen
IPC分类号： H01L23/544 , G01R27/14 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002
摘要： A method and test site for monitoring the extent of buried contact trench formation in MOS FET integrated circuit wafers is described. A number of doped silicon parallel first test electrodes are formed in test site regions of a wafer and connected in series. The test site regions are located in the spaces between chip regions of the wafer. A layer of gate oxide is then deposited over the wafer. Test openings over the first test electrodes and buried contact openings are etched in the gate oxide layer at the same time. The test openings have the same size and shape as the buried contact openings. After polysilicon and metal silicide is deposited a photoresist mask is formed to etch the buried contact electrodes, the gate electrodes, and second test electrodes which are located directly above the test openings. Any misalignment in the photoresist mask will cause trenches to be formed in the first test electrodes as well as the formation of buried contact trenches. These trenches in the first test electrodes will cause an increase the resistance of the first test electrodes which is related to the extent of the buried contact trenches. The first test electrodes can be oriented to measure the extent of buried contact trench formation regardless of orientation.
摘要翻译：描述了用于监测MOS FET集成电路晶片中的埋入接触沟槽形成程度的方法和测试部位。多个掺杂的硅平行的第一测试电极形成在晶片的测试位置区域并串联连接。测试位置区域位于晶片的芯片区域之间的空间中。然后在晶片上沉积一层栅极氧化物。在第一测试电极和埋入的接触开口上的测试开口同时在栅极氧化物层中被蚀刻。测试开口具有与埋入的接触开口相同的尺寸和形状。在沉积多晶硅和金属硅化物之后，形成光致抗蚀剂掩模以蚀刻位于测试开口正上方的掩埋接触电极，栅电极和第二测试电极。光致抗蚀剂掩模中的任何未对准将导致在第一测试电极中形成沟槽以及形成埋入的接触沟槽。第一测试电极中的这些沟槽将引起第一测试电极的电阻增加，其与埋入的接触沟槽的程度相关。第一测试电极可以被定向以测量埋入接触沟槽形成的程度，而不管取向如何。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式