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1. 发明授权

US08418157B2 Compiler apparatus with flexible optimization 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US08418157B2
公开(公告)日：2013-04-09
申请号：US12706329
申请日：2010-02-16
申请人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，如果转换单元和配对指令生成单元）执行来自用户的选项和编译指示的单独优化处理，遵循来自分析单元的指令等。全局区域分配单元执行优化处理，在指定要分配给全局区域的变量的最大数据大小，要分配给全局区域的变量的指定，以及关于在全局区域中未分配的变量的指定的选项和编译指示。

2. 发明申请

US20100175056A1 COMPILER APPARATUS WITH FLEXIBLE OPTIMIZATION 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US20100175056A1
公开(公告)日：2010-07-08
申请号：US12706329
申请日：2010-02-16
申请人： Hajime OGAWA , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime OGAWA , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

3. 发明授权

US07698696B2 Compiler apparatus with flexible optimization 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US07698696B2
公开(公告)日：2010-04-13
申请号：US10608040
申请日：2003-06-30
申请人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

4. 发明申请

US20080141229A1 PROCESSOR, PROGRAM CONVERSION APPARATUS, PROGRAM CONVERSION METHOD, AND COMPUTER PROGRAM 审中-公开
标题翻译：处理器，程序转换装置，程序转换方法和计算机程序
公开(公告)号：US20080141229A1
公开(公告)日：2008-06-12
申请号：US11969083
申请日：2008-01-03
申请人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
发明人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
IPC分类号： G06F9/45 , G06F9/312
CPC分类号： G06F9/30094 , G06F9/30021 , G06F9/30072
摘要： The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional new condition flag value.
摘要翻译：第一，第二和第三操作单元441至443各自根据在时钟周期的中途的时间点之前的指令执行预定的操作。当执行比较操作时，每个操作单元将结果值输出到条件标志操作单元51。条件标志操作单元51通过对（a）从条件标志寄存器46读取的值和结果值或（b）结果值本身执行逻辑运算来计算新条件标志值。条件标志操作单元51在时钟周期结束之前将新条件标志值输出到与条件指令相关的第一，第二和第三门451至453中的一个，以便控制条件新条件的无效标志值。

5. 发明授权

US07185324B2 Compiler apparatus and method for determining locations for data in memory area 有权
标题翻译：用于确定存储器区域中的数据的位置的编译器装置和方法
公开(公告)号：US07185324B2
公开(公告)日：2007-02-27
申请号：US10631960
申请日：2003-08-01
申请人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
发明人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
IPC分类号： G06F9/45 , G06F12/00 , G06F12/02
CPC分类号： G06F9/5016 , G06F8/443 , G06F9/44557
摘要： Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.
摘要翻译：公开了一种编译装置，用于生成由指令集构成的指令代码，每个指令集包括指定指示存储区中的数据项的位置的m位立即值的指令。编译装置根据一个数据属性从由多个数据项组成的组X中依次选择数据项; 并且每当选择数据项时，判断所选择的数据项是否可分配给n字节存储区（n <= 2 ^{m）。当判断为否定时，编译装置根据不同的数据属性指定所有选择的数据项中的数据项，并从组X中排除指定的数据项，并重复选择，直到剩余的所有数据项在排除指定数据项之后的组X被判断为可分配给存储区。}

6. 发明授权

US07254807B2 Program conversion apparatus, program conversion method, and computer program for executing program conversion process 有权
标题翻译：程序转换装置，程序转换方法和用于执行程序转换处理的计算机程序
公开(公告)号：US07254807B2
公开(公告)日：2007-08-07
申请号：US10315877
申请日：2002-12-10
申请人： Toshiyuki Sakata , Taketo Heishi , Hajime Ogawa , Shohei Michimoto , Shuichi Takayama
发明人： Toshiyuki Sakata , Taketo Heishi , Hajime Ogawa , Shohei Michimoto , Shuichi Takayama
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F9/44521 , G06F9/44542
摘要： A compiling unit (110) generates indefinite branch information showing that an instruction set to be selected is indefinite, instead of generating a branch instruction. A linking unit (130) generates an appropriate direct addressing branch instruction by judging whether an instruction set used at a branch source and an instruction set used at a branch destination are the same. Also, one reference instruction set is determined. The compiling unit (110) adds a mode adjusting instruction that belongs to the reference instruction set and that is for causing a branch to an instruction placed at a branch destination and for selecting the instruction set that is originally to be selected. The mode adjusting instruction provides an alternative branch destination corresponding to an original branch destination, and the compiling unit (110) generates an indirect addressing branch instruction for causing a branch to the alternative branch destination and for selecting the reference instruction set.
摘要翻译：编译单元（110）产生不确定的分支信息，表示选择的指令集是不确定的，而不是生成分支指令。链接单元（130）通过判断在分支源使用的指令集和在分支目的地使用的指令集是否相同来生成适当的直接寻址分支指令。此外，确定一个参考指令集。编译单元（110）添加属于参考指令集的模式调整指令，其用于使分支到位于分支目的地的指令，并且用于选择最初被选择的指令集。模式调整指令提供与原始分支目的地相对应的替代分支目的地，并且编译单元（110）生成用于使分支到备选分支目的地并用于选择参考指令集的间接寻址分支指令。

7. 发明申请

US20050216869A1 Compiler 有权
标题翻译：编译器
公开(公告)号：US20050216869A1
公开(公告)日：2005-09-29
申请号：US11087752
申请日：2005-03-24
申请人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F8/423 , G06F17/505
摘要： A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.
摘要翻译：尽管在硬件设计中输入编程语言的描述是不可能的，但是使用现有编程语言来描述特定硬件模块的编译器装置。在头文件24中，定义了难以形容的编程语言中的特定硬件。并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码硬件。

8. 发明授权

US07350165B2 Compiler 有权
标题翻译：编译器
公开(公告)号：US07350165B2
公开(公告)日：2008-03-25
申请号：US11087752
申请日：2005-03-24
申请人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F8/423 , G06F17/505
摘要： A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.
摘要翻译：编译装置能够描述现有编程语言中的特定硬件模块，尽管在硬件设计中输入编程语言的描述是不可能的。在头文件24中，定义了难以形容的编程语言中的特定硬件。并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码硬件。

9. 发明申请

US20060150135A1 Circuit information generating apparatus and circuit information generating method 审中-公开
标题翻译：电路信息生成装置及电路信息生成方法
公开(公告)号：US20060150135A1
公开(公告)日：2006-07-06
申请号：US11290806
申请日：2005-12-01
申请人： Tomoo Hamada , Hajime Ogawa , Ryoko Miyachi , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Tomoo Hamada , Hajime Ogawa , Ryoko Miyachi , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure information defining a structure of a function and the execution sequence information defining an execution sequence of the function; a structure information generating unit operable to generate, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence; a gated clock information generating unit operable to generate, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary; and an outputting unit operable to output the gated clock information together with the circuit structure information.
摘要翻译：提供了一种用于自动生成电路设计信息时钟门控的装置，用于减轻设计者对电路执行时钟门控的负担。该装置具有可从外部获取功能结构信息和执行序列信息的获取单元，定义功能结构的功能结构信息和定义功能的执行顺序的执行顺序信息; 结构信息生成单元，用于根据执行顺序信息和功能结构信息生成根据执行顺序定义执行功能的多个电路的寄存器传送等级的电路结构信息; 门控时钟信息生成单元，其可操作以根据执行顺序信息和功能结构信息生成寄存器传送级别中的门控时钟信息，其定义时钟控制电路，该时钟控制电路向至少一个电路中的每一个提供门控当不需要时钟输入时，设置为暂停时钟输入的时钟; 以及输出单元，用于将门控时钟信息与电路结构信息一起输出。

10. 再颁专利

USRE45199E1 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：USRE45199E1
公开(公告)日：2014-10-14
申请号：US13616573
申请日：2012-09-14
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

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