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1. 发明授权

US07920002B2 Pulse synthesis circuit 有权
标题翻译：脉冲合成电路
公开(公告)号：US07920002B2
公开(公告)日：2011-04-05
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K5/01
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

2. 发明申请

US20080315933A1 PULSE SYNTHESIS CIRCUIT 有权
标题翻译：脉冲合成电路
公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

3. 发明授权

US07298219B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07298219B2
公开(公告)日：2007-11-20
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

4. 发明申请

US20060139106A1 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US20060139106A1
公开(公告)日：2006-06-29
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

5. 发明授权

US06995607B2 Low-pass filter and feedback system 失效
标题翻译：低通滤波器和反馈系统
公开(公告)号：US06995607B2
公开(公告)日：2006-02-07
申请号：US10799716
申请日：2004-03-15
申请人： Shiro Dosho , Takashi Morie , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kazuaki Sogawa
IPC分类号： H03K5/00
CPC分类号： H03H7/06 , H03H11/1213 , H03H11/126 , H03H11/405 , H03L7/0893 , H03L7/093
摘要： In a low-pass filter, the filter characteristics equivalent to those of a conventional low-pass filter are maintained, the size of a capacitive element is decreased, and the low-pass filter operates stably. Further, a MOS capacitor is used as a capacitive element. For such purposes, in a low-pass filter including a first capacitive element, and a resistive element and a second capacitive element which are connected in series to the first capacitive element, a first electric current is supplied to the first input terminal connected to one end of the first capacitive element, and a second electric current is supplied to the second input terminal connected to the other end of the first capacitive element. Herein, the capacitance value of the first capacitive element is set according to the magnitude of the first electric current. Further, the resistive element is provided with a power supply that is connected in series to the resistive element, and a voltage equal to or higher than the threshold voltage of a MOS transistor is always applied between the second input terminal and the ground.
摘要翻译：在低通滤波器中，保持与传统低通滤波器相同的滤波特性，电容元件的尺寸减小，低通滤波器稳定地工作。此外，使用MOS电容器作为电容元件。为了这样的目的，在包括与第一电容元件串联连接的第一电容元件和电阻元件和电阻元件和第二电容元件的低通滤波器中，向连接到第一电容元件的第一输入端子提供第一电流第一电容元件的端部，并且第二电流被提供给连接到第一电容元件的另一端的第二输入端子。这里，第一电容元件的电容值根据第一电流的大小来设定。此外，电阻元件设置有与电阻元件串联连接的电源，并且在第二输入端子和地之间始终施加等于或高于MOS晶体管的阈值电压的电压。

6. 发明授权

US07978013B2 Phase synchronizing circuit 有权
标题翻译：相位同步电路
公开(公告)号：US07978013B2
公开(公告)日：2011-07-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

7. 发明申请

US20090278614A1 PHASE SYNCHRONIZING CIRCUIT 有权
标题翻译：相位同步电路
公开(公告)号：US20090278614A1
公开(公告)日：2009-11-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/08
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

8. 发明授权

US07323942B2 Dual loop PLL, and multiplication clock generator using dual loop PLL 有权
标题翻译：双环PLL和乘法时钟发生器使用双环PLL
公开(公告)号：US07323942B2
公开(公告)日：2008-01-29
申请号：US11320848
申请日：2005-12-30
申请人： Takashi Ishizaka , Kazuaki Sogawa
发明人： Takashi Ishizaka , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L7/087
CPC分类号： H03L7/113 , H03L7/0891 , H03L7/18
摘要： To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparator 1 for comparing phases, and a frequency comparison loop having a frequency comparator 7 for comparing frequencies, wherein the frequency comparator 7 carries out frequency comparison using an input signal inputted from a calibration clock line CLcal 18, the input signal being different from a reference clock signal inputted from an external reference clock line CLex 11, the reference clock signal being used for a phase comparator 1. Moreover, multiplication clock generators are configured using the dual loop PLL.
摘要翻译：提供能够减少初始启动时的锁定时间的双环PLL，以及有助于降低功耗的乘法时钟发生器。双环路PLL包括具有相位比较环路的双环路PLL，该相位比较环路具有用于比较相位的相位比较器1和具有用于比较频率的频率比较器7的频率比较环路，其中，频率比较器7使用输入信号从校准时钟线CLcal 18输入的输入信号不同于从外部参考时钟线CLex11输入的参考时钟信号，该参考时钟信号用于相位比较器1。此外，使用双环路PLL来配置乘法时钟发生器。

9. 发明授权

US07023284B2 Dual loop phase locked loop 失效
标题翻译：双环锁相环
公开(公告)号：US07023284B2
公开(公告)日：2006-04-04
申请号：US10485861
申请日：2003-04-17
申请人： Kazuaki Sogawa , Ryoichi Suzuki
发明人： Kazuaki Sogawa , Ryoichi Suzuki
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/089 , H03L7/0891 , H03L7/0895 , H03L7/093 , H03L7/113
摘要： In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.
摘要翻译：在具有频率比较环路和相位比较环路的双环PLL中，当上/下计数器8的输入控制电路30从频率比较器7接收到UP信号时，输入控制电路30输出正值前一加/减结果值的1/2。当输入控制电路30从频率比较器7接收到DOWN信号时，输入控制电路30输出前一加/减结果值的1/2的负值。寄存器33存储计数值。加法器31将输入控制电路30的输出与寄存器33的输出相加。因此，向上/向下计数器8以先前加/减结果值的1/2值递增或减小，并且双环PLL基于二分法搜索方法进行频率比较。因此，即使在输出频率高的情况下，也能够有效地进行频率比较，从而降低锁定时间。

10. 发明授权

US08106691B2 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US08106691B2
公开(公告)日：2012-01-31
申请号：US13206182
申请日：2011-08-09
申请人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada
发明人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0996 , H03L7/23
摘要： In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.
摘要翻译：在将双频时钟的频率除以获得50％的占空比时钟的相位调整电路中，具有相位反转功能的第一½分频电路产生相位分离的中间参考时钟，相位参考时钟和相位调整时钟。第一相位控制电路相对于相位参考时钟控制中间参考时钟的相位处于期望的相位状态。第二相位控制电路将相位调整时钟的相位相对于中间参考时钟控制在期望的相位状态。因此，当相位调整时钟被调整为与相位基准时钟相位近似时，即使由于时钟抖动而改变，这些时钟之间的相位差也可以被正确和稳定地确定。

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