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1. 发明授权

US07978013B2 Phase synchronizing circuit 有权
标题翻译：相位同步电路
公开(公告)号：US07978013B2
公开(公告)日：2011-07-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

2. 发明申请

US20090278614A1 PHASE SYNCHRONIZING CIRCUIT 有权
标题翻译：相位同步电路
公开(公告)号：US20090278614A1
公开(公告)日：2009-11-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/08
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

3. 发明授权

US07298219B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07298219B2
公开(公告)日：2007-11-20
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

4. 发明申请

US20060139106A1 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US20060139106A1
公开(公告)日：2006-06-29
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

5. 发明授权

US08106691B2 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US08106691B2
公开(公告)日：2012-01-31
申请号：US13206182
申请日：2011-08-09
申请人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada
发明人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0996 , H03L7/23
摘要： In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.
摘要翻译：在将双频时钟的频率除以获得50％的占空比时钟的相位调整电路中，具有相位反转功能的第一½分频电路产生相位分离的中间参考时钟，相位参考时钟和相位调整时钟。第一相位控制电路相对于相位参考时钟控制中间参考时钟的相位处于期望的相位状态。第二相位控制电路将相位调整时钟的相位相对于中间参考时钟控制在期望的相位状态。因此，当相位调整时钟被调整为与相位基准时钟相位近似时，即使由于时钟抖动而改变，这些时钟之间的相位差也可以被正确和稳定地确定。

6. 发明申请

US20090295489A1 PLL CIRCUIT 有权
标题翻译： PLL电路
公开(公告)号：US20090295489A1
公开(公告)日：2009-12-03
申请号：US11993108
申请日：2007-03-29
申请人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada , Junji Nakatsuka
发明人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada , Junji Nakatsuka
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/0896 , H03L7/18 , H03L2207/06
摘要： In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4. As a result, time-varying fluctuations in the voltage of the loop filter resulting from a structure in which the input terminal for evaluating the oscillation characteristics of the voltage controlled oscillator is connected to the loop filter via a switch and time-varying fluctuations in the output frequency of the PLL circuit are effectively suppressed.
摘要翻译：在PLL电路中，压控振荡器4具有两个电压 - 电流转换电路40和41以及用于选择电压 - 电流转换电路40和41中的任一个的输出的选择电路42.电压 - 电流由选择电路42选择的转换电路被输入到电流控制振荡器45.一个电压 - 电流转换电路41的输入连接到环路滤波器3的输出，而另一个电压 - 电流转换电路40具有其输入连接到用于评估压控振荡器4的振荡特性的输入端子8.结果是，由用于评估振荡特性的输入端子的结构导致的环路滤波器的电压的时变波动压控振荡器经由开关连接到环路滤波器，并且PLL电路的输出频率随时间变化被有效地抑制。

7. 发明申请

US20120286835A1 PLL CIRCUIT 审中-公开
标题翻译： PLL电路
公开(公告)号：US20120286835A1
公开(公告)日：2012-11-15
申请号：US13555674
申请日：2012-07-23
申请人： Yuji Yamada , Masayoshi Kinoshita , Kazuaki Sogawa
发明人： Yuji Yamada , Masayoshi Kinoshita , Kazuaki Sogawa
IPC分类号： H03L7/08
CPC分类号： H03L7/104 , H03L1/00 , H03L7/183
摘要： A PLL circuit includes: a frequency division section; a phase detector configured to detect the phase difference between a reference clock signal and an output signal of the frequency division section; a loop filter configured to filter an output signal of the phase detector and output the result as a digital value; a selector configured to select either the digital value or a fixed value; a digitally controlled oscillator configured to oscillate at a frequency corresponding to the value selected by the selector; and a control section configured to instruct the selector to select the fixed value until receiving a start signal, and after receiving the start signal, instruct the selector to select the digital value, and the frequency division section to start output, at timing of an edge of the reference clock signal.
摘要翻译： PLL电路包括：分频部分; 相位检测器，被配置为检测参考时钟信号和分频部分的输出信号之间的相位差; 环路滤波器，被配置为对所述相位检测器的输出信号进行滤波，并输出所述结果作为数字值; 被配置为选择数字值或固定值的选择器; 数字控制振荡器，被配置为以对应于由选择器选择的值振荡的频率; 以及控制部，被配置为指示选择器直到接收到开始信号来选择固定值，并且在接收到开始信号之后，在边缘的定时指示选择器选择数字值，并且分频部分开始输出的参考时钟信号。

8. 发明申请

US20110012664A1 CLOCK SIGNAL AMPLIFIER CIRCUIT 审中-公开
标题翻译：时钟信号放大器电路
公开(公告)号：US20110012664A1
公开(公告)日：2011-01-20
申请号：US12892542
申请日：2010-09-28
申请人： Masayoshi KINOSHITA , Kazuaki Sogawa , Yuji Yamada
发明人： Masayoshi KINOSHITA , Kazuaki Sogawa , Yuji Yamada
IPC分类号： H03L5/00
CPC分类号： H03K19/017545 , H03K19/018571
摘要： A clock signal amplifier circuit includes: an inverter; a coupling capacitor connected to the input of the inverter; two resistors connected in series between the power supply potential and the ground potential, a connection node of the two resistors being connected to the input of the inverter; a feedback resistor provided between the input and output of the inverter; and two switches configured to perform a same open/close operation according to a control signal, the two switches being provided on any two of a supply path of the power supply potential to the inverter, a supply path of the ground potential to the inverter, and a feedback path of the inverter via the feedback resistor.
摘要翻译：时钟信号放大电路包括：逆变器; 耦合电容器连接到逆变器的输入端; 两个电阻串联在电源电位和地电位之间，两个电阻的连接节点连接到逆变器的输入端; 在反相器的输入和输出之间提供反馈电阻; 以及两个开关，其被配置为根据控制信号执行相同的打开/关闭操作，所述两个开关设置在所述逆变器的电源电位的供给路径中的任意两个上，对所述逆变器的接地电位的供给路径，以及反馈电阻器的反馈路径。

9. 发明授权

US07808326B2 PLL circuit 有权
标题翻译： PLL电路
公开(公告)号：US07808326B2
公开(公告)日：2010-10-05
申请号：US11993108
申请日：2007-03-29
申请人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada , Junji Nakatsuka
发明人： Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada , Junji Nakatsuka
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L7/0896 , H03L7/18 , H03L2207/06
摘要： In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4. As a result, time-varying fluctuations in the voltage of the loop filter resulting from a structure in which the input terminal for evaluating the oscillation characteristics of the voltage controlled oscillator is connected to the loop filter via a switch and time-varying fluctuations in the output frequency of the PLL circuit are effectively suppressed.
摘要翻译：在PLL电路中，压控振荡器4具有两个电压 - 电流转换电路40和41以及用于选择电压 - 电流转换电路40和41中的任一个的输出的选择电路42.电压 - 电流由选择电路42选择的转换电路被输入到电流控制振荡器45.一个电压 - 电流转换电路41的输入连接到环路滤波器3的输出，而另一个电压 - 电流转换电路40具有其输入连接到用于评估压控振荡器4的振荡特性的输入端子8.结果是，由用于评估振荡特性的输入端子的结构导致的环路滤波器的电压的时变波动压控振荡器经由开关连接到环路滤波器，并且PLL电路的输出频率随时间变化被有效地抑制。

10. 发明申请

US20100244878A1 PLL BURN-IN CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译： PLL烧录电路和半导体集成电路
公开(公告)号：US20100244878A1
公开(公告)日：2010-09-30
申请号：US12521192
申请日：2007-12-20
申请人： Yuji Yamada , Masayoshi Kinoshita , Kazuaki Sogawa , Junji Nakatsuka
发明人： Yuji Yamada , Masayoshi Kinoshita , Kazuaki Sogawa , Junji Nakatsuka
IPC分类号： G01R31/02
CPC分类号： H03L7/099 , H03L7/0995
摘要： In a PLL which does not include a loop filter, an additional circuit for subjecting a voltage-controlled oscillator to a burn-in test with an appropriate oscillation frequency is realized by a less circuit configuration.A gate terminal of a diode-connected transistor (13) which has the same polarity as a voltage-to-current conversion transistor (11) in a voltage-controlled oscillator (10) is connected to a gate terminal of the transistor (11) through a switch (12a), and a current supply (14) is connected to a drain terminal of the transistor (13). By appropriately controlling the current value supplied from the current supply (14) and the size ratio between the transistor (11) and the transistor (13), a current required for performing a burn-in test can be supplied to a ring oscillator in the voltage-controlled oscillator (10).
摘要翻译：在不包括环路滤波器的PLL中，通过较少的电路配置来实现用于使压控振荡器经受适当振荡频率的老化测试的附加电路。与压控振荡器（10）中的电压 - 电流转换晶体管（11）具有相同极性的二极管连接的晶体管（13）的栅极端子连接到晶体管（11）的栅极端子，通过开关（12a），并且电流源（14）连接到晶体管（13）的漏极端子。通过适当地控制从电流源（14）提供的电流值和晶体管（11）和晶体管（13）之间的尺寸比，可以将执行老化测试所需的电流提供给环形振荡器压控振荡器（10）。

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