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1. 发明授权

US5636327A Neural network circuit 失效
标题翻译：神经网络电路
公开(公告)号：US5636327A
公开(公告)日：1997-06-03
申请号：US409949
申请日：1995-03-23
申请人： Hiroyuki Nakahira , Shiro Sakiyama , Masakatsu Maruyama , Susumu Maruno
发明人： Hiroyuki Nakahira , Shiro Sakiyama , Masakatsu Maruyama , Susumu Maruno
IPC分类号： G06N3/063 , G06F15/18
CPC分类号： G06K9/4628 , G06K9/00986 , G06N3/063
摘要： In a multilayered neural network for recognizing and processing characteristic data of images and the like by carrying out network arithmetical operations, characteristic data memories store the characteristic data of the layers. Coefficient memories store respective coupling coefficients of the layers other than the last layer. A weight memory stores weights of neurons of the last layer. Address converters carry out arithmetical operations to find out addresses of nets of the network whose coupling coefficients are significant. A table memory outputs a total coupling coefficient obtained by inter-multiplying the significant coupling coefficients read out from the coefficient memories of the layers. A cumulative operation unit performs cumulative additions of the product of the total coupling coefficient times the weight of the weight memory. Arithmetical operations are carried out only on particular nets with a significant coupling coefficient value. The speed of operation and recognition can be improved.
摘要翻译：在通过进行网络算术运算来识别和处理图像等的特征数据的多层神经网络中，特征数据存储器存储层的特征数据。系数存储器存储不同于最后层的层的相应耦合系数。体重记忆存储最后层的神经元的权重。地址转换器进行算术运算，找出耦合系数很大的网络网络地址。表存储器输出通过相互乘以从层的系数存储器读出的有效耦合系数而获得的总耦合系数。累积操作单元执行总耦合系数乘以权重存储器的权重的乘积的累积加法。仅对具有显着耦合系数值的特定网络进行算术运算。可以提高运行和识别的速度。

2. 发明授权

US5621862A Information processing apparatus for implementing neural network 失效
标题翻译：用于实现神经网络的信息处理设备
公开(公告)号：US5621862A
公开(公告)日：1997-04-15
申请号：US281683
申请日：1994-07-28
申请人： Hiroyuki Nakahira , Masakatsu Maruyama , Shiro Sakiyama , Susumu Maruno , Toshiyuki Kouda , Masaru Fukuda
发明人： Hiroyuki Nakahira , Masakatsu Maruyama , Shiro Sakiyama , Susumu Maruno , Toshiyuki Kouda , Masaru Fukuda
IPC分类号： G06K9/66 , G06N3/08 , G06N3/10 , G06F15/18
CPC分类号： G06K9/00986 , G06K9/6267 , G06N3/082 , G06N3/10
摘要： In an information processing apparatus for implementing a neural network, if an input vector is inputted to a calculating unit, a neuron which responds to the input vector is retrieved in accordance with network interconnection information stored in a first storage unit and the neuron number indicating the retrieved neuron is written in a first register. The calculating unit reads out the internal information of the neuron stored in a second storage unit by using the neuron number, writes it in a second register, and calculates the sum of products of the outputs of the neurons and the connection loads of synapses connected to the neurons. By repeating the sequence of operations by the number of times corresponding to the total number of input vectors, a recognition process is executed. The neural network can easily be expanded by rewriting the contents of the first and second storage units.
摘要翻译：在用于实现神经网络的信息处理装置中，如果将输入向量输入到计算单元，则根据存储在第一存储单元中的网络互连信息来检索响应于输入向量的神经元，并且指示检索到的神经元被写入第一个寄存器。计算单元通过使用神经元号读取存储在第二存储单元中的神经元的内部信息，将其写入第二寄存器，并且计算神经元的输出和连接到的突触的连接负载的乘积之和神经元。通过将操作序列重复与输入向量的总数相对应的次数，执行识别处理。可以通过重写第一和第二存储单元的内容来容易地扩展神经网络。

3. 发明授权

US5452402A Neural network circuit for adaptively controlling the coupling of neurons 失效
标题翻译：用于自适应控制神经元耦合的神经网络电路
公开(公告)号：US5452402A
公开(公告)日：1995-09-19
申请号：US155865
申请日：1993-11-23
申请人： Shiro Sakiyama , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Kouda , Susumu Maruno
发明人： Shiro Sakiyama , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Kouda , Susumu Maruno
IPC分类号： G06F15/18 , G06N3/04 , G06N3/08 , G06N99/00 , G06T7/00 , G06F15/00
CPC分类号： G06K9/62 , G06N3/08 , G06N3/082
摘要： In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit. Thus, the neural network circuit for recognizing an image or the like can execute recognition and learning of data to be recognized at high speed with small circuit size, and the recognition accuracy for unlearned data is high.
摘要翻译：在设置有具有输入向量的输入层的多层神经网络电路中，具有树状结构的网络的中间层，其输出必须由输入向量的值决定，其数量对应于输入向量的数量以及输出层，具有用于积分中间层的所有输出的多个输出单元，所述输出层是用于存储中间层和各个输出单元之间的路径中学习次数的学习时间存储器，阈值处理用于对倾斜时间存储器的输出进行阈值处理的电路和由用于控制中间层和输出单元之间的路径连接的阈值处理电路的输出来控制的连接控制电路。由连接控制电路连接的中间层的输出在每个输出单元中相加。因此，用于识别图像等的神经网络电路可以以较小的电路尺寸执行高速识别的数据的识别和学习，并且未被读取的数据的识别精度高。

4. 发明授权

US5550544A Signal converter, noise shaper, AD converter and DA converter 失效
标题翻译：信号转换器，噪声整形器，AD转换器和DA转换器
公开(公告)号：US5550544A
公开(公告)日：1996-08-27
申请号：US200493
申请日：1994-02-23
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/424 , H03M3/456
摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.
摘要翻译：本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度进入量化器并且其输出信号很小。因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。

5. 发明授权

US6067536A Neural network for voice and pattern recognition 失效
标题翻译：用于语音和模式识别的神经网络
公开(公告)号：US6067536A
公开(公告)日：2000-05-23
申请号：US864938
申请日：1997-05-29
申请人： Masakatsu Maruyama , Hiroyuki Nakahira , Masaru Fukuda , Shiro Sakiyama
发明人： Masakatsu Maruyama , Hiroyuki Nakahira , Masaru Fukuda , Shiro Sakiyama
IPC分类号： G06K9/66 , G06N3/063 , G06E1/00
CPC分类号： G06K9/6267 , G06K9/00986 , G06N3/063
摘要： A neural network circuit for performing a processing of recognizing voices, images and the like comprises a weight memory for holding a lot of weight values (initial weight values) which correspond to a plurality of input terminals of each of a plurality of neurons forming a neural network and have been initially learned, and a difference value memory for storing difference values between the weight values of the weight memory and additionally learned weight values. The weight memory is formed by a ROM. The difference value memory is formed by a SRAM, for example. During operation of recognizing input data, the initial weight values of the weight memory and the difference values of the difference value memory are added together. The added weight values are used to calculate an output value of each neuron of an output layer. Accordingly, the initial weight values can be additionally learned at a high speed by existence of the difference value memory having a small capacity. Thus, new numerals, characters and the like can be recognized well without error.
摘要翻译：用于执行识别语音，图像等的处理的神经网络电路包括用于保存与形成神经元的多个神经元中的每一个的多个输入端相对应的大量权重值（初始权重值）的权重存储器网络并且已经被初步了解，以及差值存储器，用于存储权重存储器的权重值和附加学习的权重值之间的差值。重量存储器由ROM形成。差值存储器例如由SRAM形成。在识别输入数据的操作期间，将加权存储器的初始权重值和差值存储器的差值相加在一起。加权重值用于计算输出层每个神经元的输出值。因此，通过存在具有小容量的差值存储器，可以高速地附加地学习初始权重值。因此，可以很好地识别新的数字，字符等。

6. 发明授权

US5136662A Image processor for sequential processing of successive regions of an image 失效
标题翻译：用于连续处理图像的连续区域的图像处理器
公开(公告)号：US5136662A
公开(公告)日：1992-08-04
申请号：US449194
申请日：1989-12-13
申请人： Masakatsu Maruyama , Shiro Sakiyama , Hiroyuki Nakahira , Yoshitaka Kitao , Toshiyuki Araki
发明人： Masakatsu Maruyama , Shiro Sakiyama , Hiroyuki Nakahira , Yoshitaka Kitao , Toshiyuki Araki
IPC分类号： G06T5/20
CPC分类号： G06T5/20
摘要： A local image processor is configured as a plurality of image processor elements each having a local image memory, and a single shift register circuit for supplying to the local image memories successive local images formed of an array of pixels of a source image. Each processor element includes a register holding a count value indicating the position within the source image of data that are currently being processed by that element, and the processor elements also include mutually interconnected registers whereby intermediate computation results obtained by one processor element can be utilized by another element during parallel processing operation.
摘要翻译：局部图像处理器被配置为多个具有本地图像存储器的图像处理器元件，以及单个移位寄存器电路，用于向源图像的像素阵列形成的连续的局部图像提供给局部图像存储器。每个处理器元件包括一个寄存器，该寄存器保存指示当前由该元件处理的数据的源图像内的位置的计数值，并且处理器元件还包括相互互连的寄存器，由此可以利用由一个处理器元件获得的中间计算结果并行处理操作中的另一个元素。

7. 发明授权

US06424184B1 FREQUENCY-VOLTAGE CONVERSION CIRCUIT, DELAY AMOUNT JUDGEMENT CIRCUIT, SYSTEM HAVING FREQUENCY-VOLTAGE CONVERSION CIRCUIT, METHOD OF ADJUSTING INPUT/OUTPUT CHARACTERISTICS OF FREQUENCY-VOLTAGE CONVERSION CIRCUIT, AND APPARATUS FOR AUTOMATICALLY ADJUSTING INPUT 失效
标题翻译：频率转换电路，延迟量判定电路，具有电压转换电路的系统，调整频率转换电路的输入/输出特性的方法以及用于自动调整输入的装置
公开(公告)号：US06424184B1
公开(公告)日：2002-07-23
申请号：US09269315
申请日：1999-03-24
申请人： Akira Yamamoto , Shiro Sakiyama , Hiroyuki Nakahira , Masaru Fukuda , Akira Matsuzawa , Shiro Dosho , Shinichi Yamamoto
发明人： Akira Yamamoto , Shiro Sakiyama , Hiroyuki Nakahira , Masaru Fukuda , Akira Matsuzawa , Shiro Dosho , Shinichi Yamamoto
IPC分类号： H03D300
CPC分类号： G01R23/06 , G06F1/3203 , Y02D10/126
摘要： A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.
摘要翻译：频率电压转换电路21接收时钟CLK作为输入，并根据时钟的频率提供电压IVdd作为输出。频率电压转换电路21的输入和输出特性被调节以基本匹配给定的输入和输出特性。

8. 发明申请

US20080318922A1 Bicyclic Pyrrole Derivatives 审中-公开
标题翻译：双环吡咯衍生物
公开(公告)号：US20080318922A1
公开(公告)日：2008-12-25
申请号：US11722037
申请日：2005-12-21
申请人： Hiroyuki Nakahira , Hidenori Kimura , Hitoshi Hochigai
发明人： Hiroyuki Nakahira , Hidenori Kimura , Hitoshi Hochigai
IPC分类号： A61K31/519 , C07D487/04 , A61K31/5377 , C07D401/04 , A61P3/10
CPC分类号： C07D487/04
摘要： Compounds represented by the general formula (I), prodrugs thereof, or pharmaceutically acceptable salts of both are provided as compounds which have high DPP-IV inhibiting activity and are improved in safety, toxicity and so on: (I) wherein the solid line and dotted line between A1 and A2 represents a double bond (A1=A2) or the like; A1 is C(R4) or the like; A2 is nitrogen atom or the like; R1 is hydrogen atom, optionally substituted alkyl group, or the like; R2 is hydrogen atom, optionally substituted alkyl group, or the like; R3 is hydrogen atom, halogen atom, or the like; R4 is hydrogen atom, hydroxyl, halogen atom, or the like; and Y is a group represented by the general formula (A) or the like; (A) [wherein m1 is 0, 1, 2 or 3; and the group (A) may be freed from R6 or substituted with one or two R6's which are each independently halogen atom or the like.]
摘要翻译：提供由通式（I）表示的化合物，其前体药物或两者的药学上可接受的盐作为具有高DPP-IV抑制活性并且具有改善的安全性，毒性等的化合物：（I）其中实线和 A1和A2之间的虚线表示双键（A1 = A2）等; A1是C（R4）等; A2是氮原子等; R1是氢原子，任选取代的烷基等; R2是氢原子，任选取代的烷基等; R3是氢原子，卤素原子等; R4是氢原子，羟基，卤素原子等; Y为由通式（A）等表示的基团。（A）[其中m1为0,1,2或3; 并且基团（A）可以被R6除去，或被一个或两个各自独立地为卤素原子的R6取代。

9. 发明申请

US20050270677A1 Write compensation circuit and signal interpolation circuit of recording device 有权
公开(公告)号：US20050270677A1
公开(公告)日：2005-12-08
申请号：US11198950
申请日：2005-08-08
申请人： Hirokuni Fujivama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujivama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B5/00 , G11B5/09 , G11B20/10 , H03K5/08 , H03K5/13
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.

10. 发明申请

US20050219985A1 Reproduced signal processor and reproduced signal processing method 审中-公开
标题翻译：再现信号处理器和再生信号处理方法
公开(公告)号：US20050219985A1
公开(公告)日：2005-10-06
申请号：US10513367
申请日：2003-09-02
申请人： Hiroyuki Nakahira
发明人： Hiroyuki Nakahira
IPC分类号： G11B20/10 , H03H17/02 , H03H17/06 , H03H21/00 , G11B5/09
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10481 , H03H17/06
摘要： As shown in FIG. 1, in the reproduced signal processing apparatus (100) of the present invention, the pattern predictor (103) predicts a predicted value which is a data sequence of a reproduced signal X and judges whether the predicted value matches a previously set specific pattern or not, and the adaptive equalizer (110) performs adaptive equalization on the reproduced signal X with timely updating the coefficients W of the digital filter according to the judgement result from the pattern predictor (103), and the selection circuit (104) outputs one of the output from the adaptive equalizer (110) and the predicted value as a waveform-equalized output Y on the basis of the judgement result. The reproduced signal processing apparatus (100) so constructed can realize optimal waveform equalization for coping with the non-linear distortion included in the reproduced signal.
摘要翻译：如图所示。如图1所示，在本发明的再现信号处理装置（100）中，模式预测器（103）预测作为再现信号X的数据序列的预测值，并且判断预测值是否与预先设定的特定模式匹配，并且自适应均衡器（110）根据来自模式预测器（103）的判断结果及时更新数字滤波器的系数W，对再现信号X执行自适应均衡，并且选择电路（104）输出根据判断结果，将自适应均衡器（110）的输出和预测值作为波形均衡输出Y输出。这样构成的再现信号处理装置（100）可以实现最佳的波形均衡，以应对包含在再生信号中的非线性失真。

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