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1. 发明授权

US06909644B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06909644B2
公开(公告)日：2005-06-21
申请号：US09791815
申请日：2001-02-26
申请人： Shinya Fujioka , Hitoshi Ikeda , Masato Matsumiya
发明人： Shinya Fujioka , Hitoshi Ikeda , Masato Matsumiya
IPC分类号： G11C11/409 , G11C11/00 , G11C11/401 , G11C11/405 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/065 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/002 , G11C2207/005 , G11C2211/4013
摘要： The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.
摘要翻译：本发明提供一种双存储型半导体存储器件，其具有实现更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。该半导体存储器件包括成对的位线，连接到每对位线的读出放大器，连接到每对位线的一个位线的第一存储器单元，连接到另一个位的第二存储器单元并且存储存储在第一存储单元中的数据的反相数据。该半导体存储器件的特征在于没有将位线预充电到预定电位的装置。本发明的半导体存储器件的特征还在于包括控制电路，其控制读出放大器在开始上拉操作之后开始下拉操作。

2. 发明授权

US06344990B1 DRAM for storing data in pairs of cells 有权
标题翻译：用于将数据存储在单元格对中的DRAM
公开(公告)号：US06344990B1
公开(公告)日：2002-02-05
申请号：US09652015
申请日：2000-08-31
申请人： Masato Matsumiya , Shinya Fujioka , Kimiaki Satoh , Toru Miyabo
发明人： Masato Matsumiya , Shinya Fujioka , Kimiaki Satoh , Toru Miyabo
IPC分类号： G11C506
CPC分类号： G11C7/02 , G11C7/1042 , G11C7/18 , G11C11/406 , G11C11/4097 , G11C2211/4013
摘要： A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third bit lines, and a second word line group, connected to a pair of memory cells associated with a second bit line pair including second and fourth bit lines. First and second sense amplifier groups are positioned one on each side of the memory array, and are connected to the first and second bit line pair, respectively. When any word line of the first word line group is driven, the first sense amplifier group is activated to drive the first word line group in reverse phase, and the second sense amplifier group is kept in the inactive state to keep the second word line group at the precharge level.
摘要翻译：一种包括存储单元阵列的存储电路。存储单元阵列具有连接到与包括第一和第三位线的第一位线对相关联的一对存储器单元的第一字线组，以及连接到与第二位相关联的一对存储器单元的第二字线组包括第二和第四位线的线对。第一和第二读出放大器组分别位于存储器阵列的每一侧上，并且分别连接到第一和第二位线对。当驱动第一字线组的任何字线时，第一读出放大器组被激活以反相驱动第一字线组，并且第二读出放大器组保持在非活动状态以保持第二字线组在预充电水平。

3. 发明授权

US07848176B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07848176B2
公开(公告)日：2010-12-07
申请号：US12428828
申请日：2009-04-23
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

4. 发明授权

US07730232B2 Data transfer method and system 失效
标题翻译：数据传输方式和系统
公开(公告)号：US07730232B2
公开(公告)日：2010-06-01
申请号：US11113181
申请日：2005-04-25
申请人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
发明人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F2212/2022 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C16/06 , G11C16/3454
摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.
摘要翻译：提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从响应于确认完成数据传送的传送状态。

5. 发明申请

US20060256642A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060256642A1
公开(公告)日：2006-11-16
申请号：US11488024
申请日：2006-07-18
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也可以顺序地访问字线的切换操作。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

6. 发明授权

US07102960B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07102960B2
公开(公告)日：2006-09-05
申请号：US11114087
申请日：2005-04-26
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

7. 发明授权

US06700816B2 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless 有权
标题翻译：半导体存储装置进行后期写入操作并且控制测试读取操作以不是从数据锁存电路而是从存储器核心电路读取数据，而不管前面的地址和当前地址是否彼此匹配
公开(公告)号：US06700816B2
公开(公告)日：2004-03-02
申请号：US10287495
申请日：2002-11-05
申请人： Yoshitaka Takahashi , Hitoshi Ikeda , Shinya Fujioka
发明人： Yoshitaka Takahashi , Hitoshi Ikeda , Shinya Fujioka
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1045 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/00 , G11C8/06
摘要： A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.
摘要翻译：半导体存储装置进行后期写入操作。半导体存储装置包括：存储数据的存储器核心电路; 数据锁存电路，存储对应于先前的写入操作的先前数据; 比较与前一写入操作相对应的前一地址和对应于当前读操作的当前地址的地址比较电路，以便确定前一地址和当前地址是否彼此匹配; 和控制电路。无论前一地址和当前地址是否彼此匹配，控制电路控制测试读取操作以从存储器核心电路读取数据。

8. 发明授权

US07570541B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07570541B2
公开(公告)日：2009-08-04
申请号：US11488024
申请日：2006-07-18
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

9. 发明授权

US06724675B2 Semiconductor memory device and electronic apparatus 有权
标题翻译：半导体存储器件和电子设备
公开(公告)号：US06724675B2
公开(公告)日：2004-04-20
申请号：US10352985
申请日：2003-01-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

10. 发明授权

US06396758B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06396758B2
公开(公告)日：2002-05-28
申请号：US09793603
申请日：2001-02-27
申请人： Hitoshi Ikeda , Tatsuya Kanda , Yoshitaka Takahashi , Shinya Fujioka , Akihiro Funyu
发明人： Hitoshi Ikeda , Tatsuya Kanda , Yoshitaka Takahashi , Shinya Fujioka , Akihiro Funyu
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.
摘要翻译：具有自刷新操作的半导体存储器件包括检测电路，当检测到给定输入信号的变化时产生检测信号;以及比较器电路，将检测信号与内部产生的刷新请求信号进行比较，并生成表示电路操作。

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