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1. 发明授权

US06724675B2 Semiconductor memory device and electronic apparatus 有权
标题翻译：半导体存储器件和电子设备
公开(公告)号：US06724675B2
公开(公告)日：2004-04-20
申请号：US10352985
申请日：2003-01-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

2. 发明授权

US06535950B1 Semiconductor memory device having a refresh operation 有权
标题翻译：具有刷新操作的半导体存储器件
公开(公告)号：US06535950B1
公开(公告)日：2003-03-18
申请号：US09536988
申请日：2000-03-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C114093
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

3. 发明授权

US06735141B2 Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
标题翻译：在单个芯片上具有SRAM和DRAM的半导体存储器件
公开(公告)号：US06735141B2
公开(公告)日：2004-05-11
申请号：US09917913
申请日：2001-07-31
申请人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
发明人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
IPC分类号： G11C700
CPC分类号： G11C11/005
摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
摘要翻译：半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。在芯片上提供DRAM，DRAM包括DRAM单元阵列。地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

4. 发明授权

US06292426B1 Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
标题翻译：在单个芯片上具有SRAM和DRAM的半导体存储器件
公开(公告)号：US06292426B1
公开(公告)日：2001-09-18
申请号：US09531498
申请日：2000-03-21
申请人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
发明人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
IPC分类号： G11C800
CPC分类号： G11C11/005
摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
摘要翻译：半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。在芯片上提供DRAM，DRAM包括DRAM单元阵列。地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

5. 发明授权

US06185149B2 Semiconductor integrated circuit memory 有权
标题翻译：半导体集成电路存储器
公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译：半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块长度。从上述一个或多个存储单元块读取数据。

6. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

7. 发明授权

US06172938B2 Electronic instrument and semiconductor memory device 有权
标题翻译：电子仪器和半导体存储器件
公开(公告)号：US06172938B2
公开(公告)日：2001-01-09
申请号：US09338597
申请日：1999-06-23
申请人： Takaaki Suzuki , Masao Taguchi , Kotoku Sato
发明人： Takaaki Suzuki , Masao Taguchi , Kotoku Sato
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4076
摘要： An electronic instrument includes a memory device, clock lines through which complementary clock signals are transmitted to be used for synchronization of a data output operation and a data input operation for the memory device, and strobe signal lines through which a first output strobe signal, a second output strobe signal, a first input strobe signal and a second input strobe signal are transmitted to be used to settle output data from the memory device in the data output operation and to settle input data supplied to the memory device, the first and second output strobe signals being in complementary relation to each other, the first and second input strobe signals being in complementary relation to each other.
摘要翻译：一种电子仪器，包括：存储器件，传输互补时钟信号的时钟线，用于数据输出操作的同步和存储器件的数据输入操作;以及选通信号线，第一输出选通信号，发送第二输出选通信号，第一输入选通信号和第二输入选通信号，以在数据输出操作中用于建立来自存储器件的输出数据，并且提供提供给存储器件的输入数据，第一和第二输出选通信号彼此互补，第一和第二输入选通信号彼此互补。

8. 发明授权

US06459641B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06459641B2
公开(公告)日：2002-10-01
申请号：US09834945
申请日：2001-04-16
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译：本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元，生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

9. 发明授权

US06246620B1 Semiconductor memory device 有权
公开(公告)号：US06246620B1
公开(公告)日：2001-06-12
申请号：US09533759
申请日：2000-03-23
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

10. 发明授权

US6088291A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6088291A
公开(公告)日：2000-07-11
申请号：US147600
申请日：1999-01-29
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/408 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/06 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。第WO98 / 56004号公报日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元，生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

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