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1. 发明申请

US20080021689A1 Method for designing semiconductor integrated circuit and method of circuit simulation 审中-公开
标题翻译：半导体集成电路设计方法及电路仿真方法
公开(公告)号：US20080021689A1
公开(公告)日：2008-01-24
申请号：US11812705
申请日：2007-06-21
申请人： Kyoji Yamashita , Daisaku Ikoma , Yasuyuki Sahara , Katsuhiro Ootani , Shinji Watanabe
发明人： Kyoji Yamashita , Daisaku Ikoma , Yasuyuki Sahara , Katsuhiro Ootani , Shinji Watanabe
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036
摘要： By using, as a model expression, an expression showing an inverse proportion between a change rate ΔIdsat/Idsat of saturated current value and a product of a gate protrusion length E1 and a gate width Wg of a transistor and a coefficient, modeling is executed for a transistor property that depends on the gate protrusion length. This provides a circuit simulation that takes into consideration the gate protrusion length of a gate electrode.
摘要翻译：通过使用作为模型表达式，表示在饱和电流值的变化率DeltaIdsat / Idsat与栅极突起长度E 1与晶体管的栅极宽度Wg的乘积与系数之间成反比的表达式，进行建模对于取决于栅极突起长度的晶体管性质。这提供了考虑栅电极的栅极突起长度的电路模拟。

2. 发明授权

US07476957B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07476957B2
公开(公告)日：2009-01-13
申请号：US11979669
申请日：2007-11-07
申请人： Shinji Watanabe , Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
发明人： Shinji Watanabe , Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
IPC分类号： H01L21/26
CPC分类号： H01L27/0207 , H01L21/82385 , H01L21/823892 , H01L27/0922
摘要： An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
摘要翻译：集成电路包括：第一导电类型的第一阱; 第二导电类型的第二阱在沿栅极长度方向延伸的阱边界处与第一阱接触; 第一晶体管，具有设置在第一阱中的第二导电类型的第一有源区; 以及第二晶体管，其具有设置在第一阱中的第二导电类型的第二有源区，并且与栅极宽度方向上的第一有源区的长度不同。第一有源区域在栅极宽度方向上的中心位置与第二有源区域相对于阱边界在栅极宽度方向上的中心位置对准。

3. 发明申请

US20070111405A1 Design method for semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路设计方法
公开(公告)号：US20070111405A1
公开(公告)日：2007-05-17
申请号：US11518199
申请日：2006-09-11
申请人： Shinji Watanabe , Kyoji Yamashita , Katsuhiro Ootani
发明人： Shinji Watanabe , Kyoji Yamashita , Katsuhiro Ootani
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L27/0207 , H01L27/11807
摘要： In a standard cell in which an active area and a gate conductor are provided, the active area has a largest length in a gate width direction at an end thereof in a gate length direction.
摘要翻译：在设置有源区和栅极导体的标准单元中，有源区在栅极长度方向的端部具有栅极宽度方向上的最大长度。

4. 发明申请

US20080142898A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20080142898A1
公开(公告)日：2008-06-19
申请号：US11979669
申请日：2007-11-07
申请人： Shinji Watanabe , Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
发明人： Shinji Watanabe , Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
IPC分类号： H01L27/092
CPC分类号： H01L27/0207 , H01L21/82385 , H01L21/823892 , H01L27/0922
摘要： An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
摘要翻译：集成电路包括：第一导电类型的第一阱; 第二导电类型的第二阱在沿栅极长度方向延伸的阱边界处与第一阱接触; 第一晶体管，具有设置在第一阱中的第二导电类型的第一有源区; 以及第二晶体管，其具有设置在第一阱中的第二导电类型的第二有源区，并且与栅极宽度方向上的第一有源区的长度不同。第一有源区域在栅极宽度方向上的中心位置与第二有源区域相对于阱边界在栅极宽度方向上的中心位置对准。

5. 发明申请

US20080072199A1 Method for designing semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路设计方法
公开(公告)号：US20080072199A1
公开(公告)日：2008-03-20
申请号：US11709749
申请日：2007-02-23
申请人： Kyoji Yamashita , Daisaku Ikoma , Shinji Watanabe , Katsuhiro Ootani
发明人： Kyoji Yamashita , Daisaku Ikoma , Shinji Watanabe , Katsuhiro Ootani
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The effective distance Deff_i between a well boundary and an active region of a transistor is used as a parameter for expressing a well proximity effect. For example, a delay library is created using the rising time Tslew of a signal input to the gate, load capacitance Cload at the output side and Deff_i. The use of the effective distance Deff_i between the well boundary and the transistor allows very simple modeling to be accurately performed, so that a gate-level simulation considering a well proximity effect at an LSI level is enabled.
摘要翻译：使用晶体管的阱边界和有源区之间的有效距离Deff_i作为用于表示良好邻近效应的参数。例如，使用输入到门的信号的上升时间Tslew，输出侧的负载电容Cload和Deff_i来创建延迟库。在井边界和晶体管之间使用有效距离Deff_i允许精确地执行非常简单的建模，使得考虑到在LSI级别的良好邻近效应的栅极级仿真是可以实现的。

6. 发明申请

US20080077378A1 Circuit simulation method and circuit simulation apparatus 有权
标题翻译：电路仿真方法及电路仿真装置
公开(公告)号：US20080077378A1
公开(公告)日：2008-03-27
申请号：US11822781
申请日：2007-07-10
申请人： Daisaku Ikoma , Kyoji Yamashita , Yasuyuki Sahara , Katsuhiro Ootani , Tomoyuki Ishizu
发明人： Daisaku Ikoma , Kyoji Yamashita , Yasuyuki Sahara , Katsuhiro Ootani , Tomoyuki Ishizu
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译：电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元使用与模型参数相关联的模拟程序。模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。

7. 发明授权

US07709900B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07709900B2
公开(公告)日：2010-05-04
申请号：US11892053
申请日：2007-08-20
申请人： Daisaku Ikoma , Atsuhiro Kajiya , Katsuhiro Ootani , Kyoji Yamashita
发明人： Daisaku Ikoma , Atsuhiro Kajiya , Katsuhiro Ootani , Kyoji Yamashita
IPC分类号： H01L23/62
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/0207
摘要： A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
摘要翻译：半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸方向; 以及覆盖所述栅电极的层间绝缘膜。半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。

8. 发明申请

US20060271902A1 Semiconductor integrated circuit designing method and library designing method 审中-公开
标题翻译：半导体集成电路设计方法和图书馆设计方法
公开(公告)号：US20060271902A1
公开(公告)日：2006-11-30
申请号：US11334506
申请日：2006-01-19
申请人： Kyoji Yamashita , Katsuhiro Ootani , Katsuya Arai , Daisaku Ikoma , Hiroki Taniguchi
发明人： Kyoji Yamashita , Katsuhiro Ootani , Katsuya Arai , Daisaku Ikoma , Hiroki Taniguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method for designing a semiconductor integrated circuit includes: a step (a) of setting basic patterns including a plurality of active region/gate patterns each including a gate and an active region and a dummy gate while taking account of patterns of gates on the respective sides of each gate; a step (b) of forming a plurality of basic pattern combinations by combining some of the basic patterns; and a step (c) of forming a standard cell by combining some of the plurality of basic pattern combinations. The plurality of basic pattern combinations include a single transistor (large width), a single transistor (small width), and parallel connected N transistors (large width), for example.
摘要翻译：一种用于设计半导体集成电路的方法包括：步骤（a），其设置包括多个有源区域/栅极图案的基本图案，每个有源区域/栅极图案包括栅极和有源区域以及伪栅极，同时考虑各个栅极的图案每个门的边; 通过组合一些基本图案形成多个基本图案组合的步骤（b）; 以及通过组合多个基本图案组合中的一些来形成标准单元的步骤（c）。多个基本图案组合包括例如单个晶体管（大宽度），单个晶体管（小宽度）和并联N个晶体管（大宽度）。

9. 发明申请

US20080042214A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080042214A1
公开(公告)日：2008-02-21
申请号：US11892053
申请日：2007-08-20
申请人： Daisaku Ikoma , Atsuhiro Kajiya , Katsuhiro Ootani , Kyoji Yamashita
发明人： Daisaku Ikoma , Atsuhiro Kajiya , Katsuhiro Ootani , Kyoji Yamashita
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/0207
摘要： A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
摘要翻译：半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸方向; 以及覆盖所述栅电极的层间绝缘膜。半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。

10. 发明申请

US20060282249A1 Circuit simulation method and circuit simulation apparatus 审中-公开
标题翻译：电路仿真方法及电路仿真装置
公开(公告)号：US20060282249A1
公开(公告)日：2006-12-14
申请号：US11349077
申请日：2006-02-08
申请人： Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
发明人： Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In designing a semiconductor integrated circuit, circuit information used for circuit simulation is extracted from measurement values of electric characteristics of a device included in TEG and parameters included in a netlist are modified using the measurement values and simulation values. Circuit simulation is carried out using the thus modified netlist to lead to a decrease in error in the circuit simulation which is caused due to difference between design dimension and actual finished dimension, thereby preventing an increase in design margin and a yield lowering by malfunction.
摘要翻译：在设计半导体集成电路时，从包含在TEG中的设备的电特性的测量值中提取用于电路仿真的电路信息，并且使用测量值和模拟值来修改网表中包括的参数。使用如此修改的网表进行电路仿真，导致由于设计尺寸和实际成品尺寸之间的差异导致的电路仿真中的误差减小，从而防止设计裕度增加和故障产生降低。

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