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1. 发明授权

US07470568B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07470568B2
公开(公告)日：2008-12-30
申请号：US11882199
申请日：2007-07-31
申请人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
发明人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , G02F1/13452 , H01L21/563 , H01L21/67138 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L24/86 , H01L2224/13144 , H01L2224/16 , H01L2224/75 , H01L2224/75251 , H01L2224/75252 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014
摘要： Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
摘要翻译：将半导体芯片上的凸极电极和薄膜基板上的引线以高精度连接在一起。考虑在半导体芯片上的突出电极和薄膜基板上的内部引线相互连接时发生的引线间距的变化，并且预先对内部引线的间距进行校正。同样地，考虑到将液晶基板上的电极和薄膜基板上的外部引线彼此连接时发生的引线间距的变化，并且预先对外部引线的间距进行校正。

2. 发明申请

US20080032453A1 Method of manufacturing a semiconductor device 有权
公开(公告)号：US20080032453A1
公开(公告)日：2008-02-07
申请号：US11882199
申请日：2007-07-31
申请人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
发明人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , G02F1/13452 , H01L21/563 , H01L21/67138 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L24/86 , H01L2224/13144 , H01L2224/16 , H01L2224/75 , H01L2224/75251 , H01L2224/75252 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014
摘要： Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

3. 发明授权

US06699737B2 Method of manufacturing a semiconductor device 有权
公开(公告)号：US06699737B2
公开(公告)日：2004-03-02
申请号：US10242720
申请日：2002-09-13
申请人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
发明人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
IPC分类号： H01L2144
CPC分类号： H01L24/81 , G02F1/13452 , H01L21/563 , H01L21/67138 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L24/86 , H01L2224/13144 , H01L2224/16 , H01L2224/75 , H01L2224/75251 , H01L2224/75252 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014
摘要： Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

4. 发明授权

US07262083B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07262083B2
公开(公告)日：2007-08-28
申请号：US10754545
申请日：2004-01-12
申请人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
发明人： Shinji Tojo , Shinya Kanamitsu , Seiichi Ichihara
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , G02F1/13452 , H01L21/563 , H01L21/67138 , H01L23/49838 , H01L23/4985 , H01L24/50 , H01L24/86 , H01L2224/13144 , H01L2224/16 , H01L2224/75 , H01L2224/75251 , H01L2224/75252 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014
摘要： Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
摘要翻译：将半导体芯片上的凸极电极和薄膜基板上的引线以高精度连接在一起。考虑在半导体芯片上的突出电极和薄膜基板上的内部引线相互连接时发生的引线间距的变化，并且预先对内部引线的间距进行校正。同样地，考虑到将液晶基板上的电极和薄膜基板上的外部引线彼此连接时发生的引线间距的变化，并且预先对外部引线的间距进行校正。

5. 发明授权

US06060770A Semiconductor device and process for producing the same 失效
公开(公告)号：US06060770A
公开(公告)日：2000-05-09
申请号：US7079
申请日：1998-01-14
申请人： Hisao Nakamura , Seiichi Ichihara , Ryosuke Kimoto , Hiroshi Kawakubo , Ryo Haruta , Hiroshi Koyama
发明人： Hisao Nakamura , Seiichi Ichihara , Ryosuke Kimoto , Hiroshi Kawakubo , Ryo Haruta , Hiroshi Koyama
IPC分类号： H01L23/28 , H01L21/56 , H01L21/60 , H01L23/495
CPC分类号： H01L24/50 , H01L23/49572 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/181
摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

6. 发明授权

US08338288B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08338288B2
公开(公告)日：2012-12-25
申请号：US13081160
申请日：2011-04-06
申请人： Tamaki Wada , Akihiro Tobita , Seiichi Ichihara
发明人： Tamaki Wada , Akihiro Tobita , Seiichi Ichihara
IPC分类号： H01L21/44
CPC分类号： H01L24/08 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/0347 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05027 , H01L2224/05164 , H01L2224/05166 , H01L2224/05553 , H01L2224/05572 , H01L2224/05644 , H01L2224/16225 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4845 , H01L2224/48453 , H01L2224/48465 , H01L2224/48644 , H01L2224/49175 , H01L2224/73265 , H01L2224/83 , H01L2224/85205 , H01L2224/85444 , H01L2224/92247 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01051 , H01L2924/01063 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/078 , H01L2924/07802 , H01L2924/10162 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.
摘要翻译：关于其中导电构件耦合到从形成在钝化膜中的开口露出的接合焊盘的表面的半导体器件，提供了能够抑制钝化膜中的裂纹的发生的技术。电极层的第一端和焊盘的第一端之间的第二平面距离大于电极层的第一端和开口的第一端之间的第一平面距离。由于电极层的第一端和焊盘的第一端之间的第二平面距离长，所以即使当电极的耦合位置偏离电极层的第一端侧时，由于将电线耦合到可以防止电极层的台阶部分传递到焊盘的第一端部。

7. 发明申请

US20120049572A1 VEHICLE BODY STRUCTURE 有权
标题翻译：车身结构
公开(公告)号：US20120049572A1
公开(公告)日：2012-03-01
申请号：US13319911
申请日：2010-05-25
申请人： Tadayoshi Hashimura , Makoto Iwasa , Seiichi Ichihara , Nobuhiro Mori , Kenji Tamura
发明人： Tadayoshi Hashimura , Makoto Iwasa , Seiichi Ichihara , Nobuhiro Mori , Kenji Tamura
IPC分类号： B60K28/14
CPC分类号： B62D25/2027 , B60L11/1816 , Y02T10/7005 , Y02T10/7072 , Y02T90/14
摘要： A vehicle body structure is provided with a vehicle body member, a charger, a structural support member. The charger includes an upper end portion and a lower end portion. The lower end portion of the charger is supported on the vehicle body member. The structural support member extends in a widthwise direction of the vehicle body structure in a position rearward of the upper end portion of the charger and adjacent the upper end portion of the charger.
摘要翻译：车身结构设置有车身构件，充电器，结构支撑构件。充电器包括上端部和下端部。充电器的下端部被支撑在车身构件上。结构支撑构件在车身结构的宽度方向上延伸在充电器的上端部的后方并与充电器的上端部相邻的位置。

8. 发明授权

US06278176B1 Semiconductor device and process for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06278176B1
公开(公告)日：2001-08-21
申请号：US09545463
申请日：2000-04-07
申请人： Hisao Nakamura , Seiichi Ichihara , Ryosuke Kimoto , Hiroshi Kawakubo , Ryo Haruta , Hiroshi Koyama
发明人： Hisao Nakamura , Seiichi Ichihara , Ryosuke Kimoto , Hiroshi Kawakubo , Ryo Haruta , Hiroshi Koyama
IPC分类号： H01L2302
CPC分类号： H01L24/50 , H01L23/49572 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00 , H01L2224/05599
摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.
摘要翻译：具有半导体芯片的带状载体封装的厚度在焊盘集中在半导体芯片的一侧上时是均匀的。磁带载体封装是这样的，即，虚拟焊盘6b布置在与半导体芯片中布置有焊盘（有效引脚）6a的一侧相对的一侧上。虚拟引线5形成在绝缘带4上。半导体芯片由连接到相应的接合焊盘6a的内部引线部分5a和连接到相应的虚设焊盘6b的虚拟引线5的内部引线部分5a支撑。

9. 发明申请

US20080090314A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080090314A1
公开(公告)日：2008-04-17
申请号：US11859243
申请日：2007-09-21
申请人： Seiichi Ichihara , Atsushi Obuchi
发明人： Seiichi Ichihara , Atsushi Obuchi
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05022 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05184 , H01L2224/05567 , H01L2224/05572 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/1147 , H01L2224/16225 , H01L2224/16227 , H01L2224/29006 , H01L2224/29082 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/3201 , H01L2224/32013 , H01L2224/32058 , H01L2224/32225 , H01L2224/81903 , H01L2224/83101 , H01L2224/8385 , H01L2224/83851 , H01L2224/9211 , H01L2924/13091 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2924/01074
摘要： It is in offering the technology which can solve the problem actualized in connection with the narrowing of a pitch of a bump electrode. Concretely, even if it is a case where the contact position of the probe needle to a bump electrode shifts, in the needle contact of the probe needle in an electrical property test, the technology in which it can prevent that a probe needle contacts an adjoining bump electrode is offered. Bump electrodes are arranged in a single line, and they are arranged so that a partial area may shift in an adjoining bump electrode. And a probe needle is contacted to the region which has shifted and an electrical property test is carried out.
摘要翻译：它提供了可以解决与突起电极的间距变窄有关的问题的技术。具体地说，即使在电气性试验中探头针与凸块电极的接触位置移动的情况下，也可以在探针接触时能够防止探针接触邻接提供凸块电极。凸起电极布置成一条线，并且它们被布置成使得部分区域可能在相邻的凸起电极中移位。并且探针与已移动的区域接触并进行电性能测试。

10. 发明授权

US5061985A Semiconductor integrated circuit device and process for producing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5061985A
公开(公告)日：1991-10-29
申请号：US364463
申请日：1989-06-12
申请人： Hideo Meguro , Yoshiaki Yoshiura , Tatsuo Itagaki , Ken Uchida , Tsuneo Satoh , Seiichi Ichihara , Koichi Nagasawa
发明人： Hideo Meguro , Yoshiaki Yoshiura , Tatsuo Itagaki , Ken Uchida , Tsuneo Satoh , Seiichi Ichihara , Koichi Nagasawa
IPC分类号： H01L23/485 , H01L23/498 , H01L23/532
CPC分类号： H01L23/485 , H01L23/49855 , H01L23/53223 , H01L2924/0002
摘要： With the reduction in the size of semiconductor integrated circuit devices, there have been increases in the resistance at the contact portions of metal interconnections and in the incidence of contact failure. To solve these problems, the present invention provides a novel interconnection structure. Namely, a metal interconnection which has a barrier metal layer formed thereunder and which is also used to form electrode lead-out portions for external connection is arranged such that, among the following portions, that is, electrode portions of a plurality of elements fabricated on a semiconductor substrate in the form of an integrated circuit, interconnection portions between these elements, and the above-described electrode lead-out portions for external connection, those portions of the interconnection layer which are defined as the electrode portions of the elements and the interconnection portions are isolated from the semiconductor substrate by means of a barrier metal layer, while those portions of the interconnection layer which are defined as the electrode lead-out portions for external connection are formed not through the barrier metal layer but directly on the interlayer insulating layer.
摘要翻译：随着半导体集成电路器件的尺寸的减小，金属互连接触部分的电阻和接触故障的发生率都有所增加。为了解决这些问题，本发明提供了一种新的互连结构。也就是说，在其下面形成有阻挡金属层并且也用于形成用于外部连接的电极引出部分的金属互连布置成使得在以下部分中，即在下列部分之中制造多个元件的电极部分集成电路形式的半导体衬底，这些元件之间的互连部分和用于外部连接的上述电极引出部分，被定义为元件的电极部分的互连层的那些部分和互连部分通过阻挡金属层与半导体基板隔离，而被定义为外部连接的电极引出部的互连层的那些部分不是通过阻挡金属层而是直接形成在层间绝缘层上。

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