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1. 发明授权

US5918063A Data driven type information processing apparatus including plural data driven type processors and plural memories 失效
标题翻译：数据驱动型信息处理装置，包括多个数据驱动型处理器和多个存储器
公开(公告)号：US5918063A
公开(公告)日：1999-06-29
申请号：US699878
申请日：1996-08-20
申请人： Ryuji Miyama , Shinichi Yoshida , Tsuyoshi Muramatsu , Souichi Miyata
发明人： Ryuji Miyama , Shinichi Yoshida , Tsuyoshi Muramatsu , Souichi Miyata
IPC分类号： G06F9/44 , G06F15/82 , G06F13/00
CPC分类号： G06F9/4436 , G06F15/82
摘要： A data flow information processing apparatus includes one or a plurality of data driven type processors for processing data packets based on a data flow program, one or a plurality of memories accessed by these processors, and a router receiving data packets processed by these data processors for selecting a path for selectively applying the data packet to any of the one or the plurality of memories. More preferably, a first router includes an address calculating unit for calculating the address based on the content of the data packet, and a branching unit for branching the path of the data packet based on the calculated address. The data packet includes a generation number allotted in accordance with the order of input time and data. The address calculating unit includes a unit for calculating a modified address by modifying the generation number based on the data. The address modifying unit may include a circuit for modifying the generation number with a prescribed global offset, and a circuit for calculating a locally offset address by further modifying the generation number with the data included in the applied data packet.
摘要翻译：数据流信息处理装置包括一个或多个数据驱动型处理器，用于基于数据流程序处理数据包，由这些处理器访问的一个或多个存储器，以及接收由这些数据处理器处理的数据包的路由器，用于选择用于选择性地将数据分组应用于一个或多个存储器中的任何一个的路径。更优选地，第一路由器包括：地址计算单元，用于基于数据分组的内容计算地址;以及分支单元，用于基于所计算的地址来分支数据分组的路径。数据包包括根据输入时间和数据的顺序分配的生成号码。地址计算单元包括通过基于该数据修改生成号码来计算修改地址的单元。地址修改单元可以包括用于以规定的全局偏移量修改发电数的电路，以及用于通过使用包含在所应用的数据包中的数据进一步修改发电数来计算本地偏移地址的电路。

2. 发明授权

US5526502A Memory interface 失效
标题翻译：内存界面
公开(公告)号：US5526502A
公开(公告)日：1996-06-11
申请号：US39760
申请日：1993-03-30
申请人： Shinichi Yoshida , Souichi Miyata , Tsuyoshi Muramatsu
发明人： Shinichi Yoshida , Souichi Miyata , Tsuyoshi Muramatsu
IPC分类号： G06F12/00 , G06F15/82 , G09G5/36 , G09G5/39 , G06F12/10 , G06F3/023
CPC分类号： G09G5/39 , G09G5/36
摘要： A memory interface device capable of memory accessing suitable for video image signal processing and memory accessing designating an arbitrary address. The interface includes an input scrambler for rewriting the generation number of an input data packet utilizing first data and/or second data when the instruction code of the input data packet is a table conversion instruction, and otherwise outputting the input data packet as it is, and a memory accessing circuit accessing an image memory using the generation number of the applied input data packet as an address and outputting the result of accessing. The device produces and outputs an output data packet from the result of accessing output from the memory accessing circuit and the input data packet.
摘要翻译：一种存储器接口设备，能够进行存储器访问，适用于指定任意地址的视频图像信号处理和存储器访问。接口包括输入扰码器，用于当输入数据分组的指令代码是表格转换指令时，利用第一数据和/或第二数据重写输入数据分组的生成数，否则直接输出输入数据分组，以及存储器访问电路，使用所施加的输入数据包的生成号作为地址访问图像存储器，并输出访问结果。该装置根据从存储器访问电路和输入数据包的输出访问结果产生输出数据包。

3. 发明授权

US5696920A Stand-alone data driven type information processor 失效
标题翻译：独立数据驱动型信息处理器
公开(公告)号：US5696920A
公开(公告)日：1997-12-09
申请号：US789691
申请日：1997-01-27
申请人： Souichi Miyata , Shinichi Yoshida , Tsuyoshi Muramatsu
发明人： Souichi Miyata , Shinichi Yoshida , Tsuyoshi Muramatsu
IPC分类号： G06F9/44 , G06F9/445 , G06F15/82
CPC分类号： G06F9/4436 , G06F9/445
摘要： A data driven type information processor includes a data driven type information processing unit, and a download unit. The information processing unit includes a program storing unit and an input/output control unit of a data packet for storing information stored in a data packet including a load instruction into the program storing unit and for carrying out a data driven type process on data packets including other instructions according to information stored in the program storing unit. The download unit downloads program data to the information processing unit by applying a data packet including the load instruction and program data to be stored in the program storing unit. The download unit includes a memory for storing program data, a readout circuit for reading out a set of program data stored in the memory, and a packet generation circuit for generating a data packet including the load instruction and readout program data to provide the same to the input/output control unit of the information processing unit. The memory may store a plurality of sets of program data.
摘要翻译：数据驱动型信息处理器包括数据驱动型信息处理单元和下载单元。信息处理单元包括程序存储单元和数据分组的输入/输出控制单元，用于存储存储在包括程序存储单元的加载指令的数据分组中的信息，并且对数据分组执行数据驱动类型处理，包括根据存储在程序存储单元中的信息的其他指令。下载单元通过应用包含要存储在程序存储单元中的加载指令和程序数据的数据分组将程序数据下载到信息处理单元。下载单元包括用于存储程序数据的存储器，用于读出存储在存储器中的一组程序数据的读出电路，以及用于产生包括加载指令和读出程序数据的数据分组的分组生成电路，以将其提供给信息处理单元的输入/输出控制单元。存储器可以存储多组节目数据。

4. 发明授权

US5577256A Data driven type information processor including a combined program memory and memory for queuing operand data 失效
标题翻译：数据驱动型信息处理器，包括组合程序存储器和用于排队操作数数据的存储器
公开(公告)号：US5577256A
公开(公告)日：1996-11-19
申请号：US53442
申请日：1993-04-28
申请人： Tsuyoshi Muramatsu , Shinichi Yoshida , Souichi Miyata
发明人： Tsuyoshi Muramatsu , Shinichi Yoshida , Souichi Miyata
IPC分类号： G06F9/44 , G06F15/82
CPC分类号： G06F9/4436
摘要： A data driven type information processor includes a control unit having a function of storing a data flow program and accessing it, and a function of producing an operand data pair, the control unit further including one memory shared by both functions. When a program is executed, program data per 1 accessing to the memory and operand data related to the program data are read out simultaneously and applied to an operation unit. Accordingly, a program memory and a memory for queuing operand data, which, were separately provided in a conventional technique, are combined into a single mechanism. Thereby, the number of stages of processing in program execution in the information processor is reduced and increase in program execution speed is permitted.
摘要翻译：数据驱动型信息处理器包括具有存储数据流程序并访问它的功能的控制单元以及产生操作数数据对的功能，所述控制单元还包括由两个功能共享的一个存储器。当执行程序时，每次访问存储器的程序数据和与程序数据相关的操作数数据被同时读出并应用于操作单元。因此，将常规技术分开提供的程序存储器和用于排队操作数数据的存储器组合成单个机构。由此，信息处理器中的程序执行中的处理的次数减少，并且允许程序执行速度的增加。

5. 发明授权

US5586281A Data driven type information processing apparatus 失效
标题翻译：数据驱动型信息处理装置
公开(公告)号：US5586281A
公开(公告)日：1996-12-17
申请号：US141207
申请日：1993-10-26
申请人： Ryuji Miyama , Shinichi Yoshida , Tsuyoshi Muramatsu , Souichi Miyata
发明人： Ryuji Miyama , Shinichi Yoshida , Tsuyoshi Muramatsu , Souichi Miyata
IPC分类号： G06F9/44 , G06F15/82 , G06F12/00
CPC分类号： G06F9/4436 , G06F15/82
摘要： A data flow information processing apparatus includes one or a plurality of data driven type processors for processing data packets based on a data flow program, one or a plurality of memories accessed by these processors, and a router receiving data packets processed by these data processors for selecting a path for selectively applying the data packet to any of the one or the plurality of memories. More preferably, a first router includes an address calculating unit for calculating the address based on the content of the data packet, and a branching unit for branching the path of the data packet based on the calculated address. The data packet includes a generation number allotted in accordance with the order of input time and data. The address calculating unit includes a unit for calculating a modified address by modifying the generation number based on the data. The address modifying unit may include a circuit for modifying the generation number with a prescribed global offset, and a circuit for calculating a locally offset address by further modifying the generation number with the data included in the applied data packet.
摘要翻译：数据流信息处理装置包括一个或多个数据驱动型处理器，用于基于数据流程序处理数据包，由这些处理器访问的一个或多个存储器，以及接收由这些数据处理器处理的数据包的路由器，用于选择用于选择性地将数据分组应用于一个或多个存储器中的任何一个的路径。更优选地，第一路由器包括：地址计算单元，用于基于数据分组的内容计算地址;以及分支单元，用于基于所计算的地址来分支数据分组的路径。数据包包括根据输入时间和数据的顺序分配的生成号码。地址计算单元包括通过基于该数据修改生成号码来计算修改地址的单元。地址修改单元可以包括用于以规定的全局偏移量修改发电数的电路，以及用于通过使用包含在所应用的数据包中的数据进一步修改发电数来计算本地偏移地址的电路。

6. 发明授权

US5392405A Data processor for detecting identical data coexisting in a plurality of data sections of data transmission paths 失效
标题翻译：用于检测在数据传输路径的多个数据段中共存的相同数据的数据处理器
公开(公告)号：US5392405A
公开(公告)日：1995-02-21
申请号：US208032
申请日：1994-03-09
申请人： Koji Komatsu , Shinichi Yoshida , Souichi Miyata , Daisuke Azuma
发明人： Koji Komatsu , Shinichi Yoshida , Souichi Miyata , Daisuke Azuma
IPC分类号： G06F7/02 , G06F9/44 , G06F13/38 , G06F13/14
CPC分类号： G06F9/4436 , G06F7/02
摘要： So-called template matching processing is function-distributed into a pre-detecting portion and a template matching portion, processing in the respective portions being achieved by a hardware circuit. In the pre-detecting portion, the relationship between data which simultaneously exist in the determined comparing sections on data transmission paths, and matching processing is performed in advance with respect to data to be matched. The template matching portion includes an addressing type general-purpose memory and performs main processing of template matching based on the result of the comparison and determination in the pre-detecting portion.
摘要翻译：所谓的模板匹配处理功能分布到预检测部分和模板匹配部分中，各部分的处理由硬件电路实现。在预检测部分中，相对于要匹配的数据，预先执行在确定的数据传输路径上的比较部分中同时存在的数据与匹配处理之间的关系。模板匹配部分包括寻址型通用存储器，并且基于预检测部分中的比较和确定的结果执行模板匹配的主要处理。

7. 发明授权

US5317756A Data processor for detecting identical data coexisting in a plurality of data section of data transmission paths 失效
标题翻译：用于检测在数据传输路径的多个数据段中共存的相同数据的数据处理器
公开(公告)号：US5317756A
公开(公告)日：1994-05-31
申请号：US779805
申请日：1991-10-21
申请人： Koji Komatsu , Shinichi Yoshida , Souichi Miyata , Daisuke Azuma
发明人： Koji Komatsu , Shinichi Yoshida , Souichi Miyata , Daisuke Azuma
IPC分类号： G06F7/02 , G06F9/44 , G06F13/00
CPC分类号： G06F9/4436 , G06F7/02
摘要： So-called template matching processing is function-distributed into a pre-detecting portion and a template matching portion, processing in the respective portions being achieved by a hardware circuit. In the pre-detecting portion, the relationship between data which simultaneously exist in the determined comparing sections on data transmission paths, and matching processing is performed in advance with respect to data to be matched. The template matching portion includes an addressing type general-purpose memory and performs main processing of template matching based on the result of the comparison and determination in the pre-detecting portion.
摘要翻译：所谓的模板匹配处理功能分布到预检测部分和模板匹配部分中，各部分的处理由硬件电路实现。在预检测部分中，相对于要匹配的数据，预先执行在确定的数据传输路径上的比较部分中同时存在的数据与匹配处理之间的关系。模板匹配部分包括寻址型通用存储器，并且基于预检测部分中的比较和确定的结果执行模板匹配的主要处理。

8. 发明授权

US5113339A Data processor for detecting identical data simultaneously coexisting in a plurality of data sections of data transmission paths 失效
标题翻译：数据处理器用于在数据传输数据段的多个数据段中同时检测标识数据
公开(公告)号：US5113339A
公开(公告)日：1992-05-12
申请号：US260061
申请日：1988-10-20
申请人： Koji Komatsu , Shinichi Yoshida , Souichi Miyata , Daisuke Azuma
发明人： Koji Komatsu , Shinichi Yoshida , Souichi Miyata , Daisuke Azuma
IPC分类号： G06F7/02 , G06F9/44 , G06F7/04 , G06F7/20 , G06F13/00
CPC分类号： G06F9/4436 , G06F7/02
摘要： So-called template matching processing is function-distributed into a pre-detecting portion and a template matching portion, processing in the respective portions being achieved by a hardware circuit. In the pre-detecting portion, the relationship between data which simultaneously exist in the determined comparing sections on data transmission paths, and matching processing is performed in advance with respect to data to be matched. The template matching portion includes an addressing type general-purpose memory and performs main processing of template matching based on the result of the comparison and determination in the pre-detecting portion.
摘要翻译：所谓的模板匹配处理功能分布到预检测部分和模板匹配部分中，各部分的处理由硬件电路实现。在预检测部分中，相对于要匹配的数据，预先执行在确定的数据传输路径上的比较部分中同时存在的数据与匹配处理之间的关系。模板匹配部分包括寻址型通用存储器，并且基于预检测部分中的比较和确定的结果执行模板匹配的主要处理。

9. 发明授权

US5093919A Data flow type information processor with plural output program storing apparatus 失效
标题翻译：具有多个输出程序存储装置的数据流型信息处理器
公开(公告)号：US5093919A
公开(公告)日：1992-03-03
申请号：US260045
申请日：1988-10-20
申请人： Shinichi Yoshida , Souichi Miyata
发明人： Shinichi Yoshida , Souichi Miyata
IPC分类号： G06F15/16 , G06F9/44 , G06F15/82
CPC分类号： G06F9/4436
摘要： A program storing portion in a data flow type information processor has one input port and two output ports. The two output ports are coupled to a paired data detecting portion through two transmission paths. A program storing portion has a copy function of generating a copy data packet from an original data packet. The original data packet is outputted to the paired data detecting portion through one of the transmission paths from one of the output ports. The copy data packet is outputted to the paired data detecting portion through the other transmission path from the other output port.
摘要翻译：数据流型信息处理器中的程序存储部分具有一个输入端口和两个输出端口。两个输出端口通过两个传输路径耦合到成对数据检测部分。程序存储部分具有从原始数据分组生成复制数据分组的复制功能。原始数据包通过来自输出端口之一的传输路径之一输出到成对数据检测部分。复制数据分组通过另一个传输路径从另一个输出端口输出到配对数据检测部分。

10. 发明授权

US5502834A Memory interface apparatus for carrying out complex operation processing 失效
标题翻译：用于执行复杂操作处理的存储器接口装置
公开(公告)号：US5502834A
公开(公告)日：1996-03-26
申请号：US215564
申请日：1994-03-22
申请人： Katsumi Arata , Shinichi Yoshida , Tsuyoshi Muramatsu
发明人： Katsumi Arata , Shinichi Yoshida , Tsuyoshi Muramatsu
IPC分类号： G06F12/00 , G06F15/82 , G09G5/393 , G06F13/12
CPC分类号： G09G5/393
摘要： A memory interface apparatus includes: a pipeline register holding a data packet from a transmission path to provide an instruction code, a generation number, and data separately; a memory access unit accessing an image memory according to the instruction code, a circuit latching the output of the image memory; an ALU carrying out an operation specified by the instruction code from the pipeline register between data from the pipeline register and the output of the latch circuit for output of the operation result; a selector responsive to a select signal for selecting one of data from the pipeline register and the output of the ALU to apply the selected result to the image memory as data; an output unit generating a data packet including a result of a series of complex operation carried out by the pipeline register, the image memory, and the ALU for output; a transmission control unit controlling transmission of a data packet on the transmission path carried out by the pipeline register and the output unit; and a control unit responsive to the instruction code from the pipeline register for controlling the ALU, the memory access unit, the image memory, the latch circuit, the selector, the output unit, and the transmission control unit so that a series of complex operation processing including an access to the image memory specified by the instruction code is carried out.
摘要翻译：存储器接口装置包括：流水线寄存器，其保存来自传输路径的数据分组以分别提供指令代码，生成号和数据; 存储器访问单元，根据指令代码访问图像存储器;锁存图像存储器的输出的电路; ALU在来自流水线寄存器的数据和锁存电路的输出之间从流水线寄存器指定的指令执行操作，以输出操作结果; 响应于选择信号的选择器，用于从流水线寄存器选择数据中的一个和ALU的输出，以将所选择的结果作为数据应用于图像存储器; 产生包括由流水线寄存器，图像存储器和ALU执行的一系列复杂操作的结果的数据分组的输出单元，用于输出; 传输控制单元，控制由流水线寄存器和输出单元执行的传输路径上的数据分组的传输; 以及控制单元，其响应来自流水线寄存器的指令代码来控制ALU，存储器存取单元，图像存储器，锁存电路，选择器，输出单元和传输控制单元，使得一系列复杂操作执行包括对由指令代码指定的图像存储器的访问的处理。

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