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    • 2. 发明授权
    • Coil component
    • 线圈组件
    • US07515028B1
    • 2009-04-07
    • US12213753
    • 2008-06-24
    • Shinichi SatoSatoshi KurimotoMakoto MoritaAkira TakashimaSumio TakahashiYoshiaki Kitajima
    • Shinichi SatoSatoshi KurimotoMakoto MoritaAkira TakashimaSumio TakahashiYoshiaki Kitajima
    • H01F5/00
    • H01F17/045H01F27/027H01F27/292H01F41/10
    • A coil component having a low profile and being conducive to high-density mounting. The coil component includes a core 2 having a coil winding portion, and first and second flanges disposed on either end of the coil winding portion. The second flange is adapted to be mounted on a circuit board, and is configured of a substantially octagonal bottom surface having first and second peripheral surfaces and first through fourth omitted peripheral surfaces. The first terminal electrode is disposed across the first omitted peripheral surface and a part of the bottom surface, and the second terminal electrode is disposed across the second omitted peripheral surface and part of the bottom surface separated from the first terminal electrode. A winding is wound over the coil winding portion and has a first end electrically connected to the first terminal electrode at the first omitted peripheral surface, and a second end electrically connected to the second terminal electrode at the second omitted peripheral surface.
    • 具有低轮廓并有利于高密度安装的线圈部件。 线圈部件包括具有线圈绕组部分的芯体2和设置在线圈绕组部分的任一端的第一和第二凸缘。 第二凸缘适于安装在电路板上,并且由具有第一和第二外围表面以及第一至第四省略的外围表面的基本上八边形的底表面构成。 第一端子电极跨越第一省略的外周表面和底表面的一部分,并且第二端子电极跨越第二省略的外围表面和与第一端子电极分离的底表面的一部分。 绕组缠绕在线圈绕组部分上,并且在第一省略的外围表面上具有与第一端子电连接的第一端,以及在第二省略的外围表面与第二端子电连接的第二端。
    • 6. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08331137B2
    • 2012-12-11
    • US13234796
    • 2011-09-16
    • Akira TakashimaReika Ichihara
    • Akira TakashimaReika Ichihara
    • G11C11/00
    • G11C11/5685G11C13/0007G11C13/003G11C13/0069G11C13/0097G11C2013/0092G11C2213/33G11C2213/76
    • According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.
    • 根据一个实施例,非易失性半导体存储器件包括存储单元,其包括可变电阻元件和串联连接在第一和第二导线之间的电容器,以及将第一和第二电压脉冲之一施加到存储单元的控制电路。 电容器由第一和第二电压脉冲之一的前沿充电,并且将第一和第二电压脉冲之一的后沿放电。 控制电路使得第一和第二电压脉冲的后沿的波形不同,通过使用第一电压脉冲将可变电阻元件的电阻值从第一电阻值改变为第二电阻值,并且改变电阻值 通过使用第二电压脉冲从第二电阻值到第一电阻值。
    • 7. 发明申请
    • SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    • 半导体器件及制造半导体器件的方法
    • US20120025294A1
    • 2012-02-02
    • US13208454
    • 2011-08-12
    • Masao SHINGUAkira TakashimaKoichi Muraoka
    • Masao SHINGUAkira TakashimaKoichi Muraoka
    • H01L29/788H01L21/336
    • H01L29/788H01L21/28273H01L21/28282H01L27/11521H01L27/11568H01L29/42324H01L29/4234H01L29/513H01L29/66825
    • There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge
    • 提供一种半导体器件,其中抑制源于上绝缘层和元件隔离绝缘层之间的界面的可靠性的劣化。 半导体器件包括:半导体区域; 多个堆叠结构,其各自设置在所述半导体区域上,并且具有依次堆叠的隧道绝缘膜,电荷存储层,上绝缘层和控制电极; 设置在所述多个堆叠结构的侧面上的元件隔离绝缘层; 以及设置在半导体区域和多个堆叠结构中的源极 - 漏极区域。 元件隔离绝缘层包括SiO 2,SiN和SiON中的至少一种,上绝缘层是含有选自稀土金属,Y,Zr和Hf中的至少一种金属M的氧化物,Si ,并且沟道长度方向上的电荷存储层,上绝缘层和控制电极的各自的长度Lcharge,Ltop和Lgate满足关系“Lcharge