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1. 发明申请

US20090046524A1 MULTI-COLUMN DECODER STRESS TEST CIRCUIT 有权
标题翻译：多列解码器应力测试电路
公开(公告)号：US20090046524A1
公开(公告)日：2009-02-19
申请号：US12168611
申请日：2008-07-07
申请人： Shin-Ho Chu , Sun-Mo An
发明人： Shin-Ho Chu , Sun-Mo An
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/02 , G11C8/10 , G11C29/024 , G11C29/025 , G11C2029/1204 , G11C2029/2602
摘要： The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals.
摘要翻译：本文描述的实施例涉及提供一种多列解码器应力测试电路，其能够通过使用列选择信号来充分执行应力测试来减少列应力测试时间。所述多列解码器应力测试电路包括被配置为接收至少一个列测试信号并产生多列使能信号的控制单元，以及多使能解码单元，被配置为接收所述多列使能信号并产生多个启用列选择信号。

2. 发明授权

US07940115B2 Fuse circuit for semiconductor integrated circuit and control method of the same 有权
标题翻译：用于半导体集成电路的保险丝电路及其控制方法相同
公开(公告)号：US07940115B2
公开(公告)日：2011-05-10
申请号：US12333181
申请日：2008-12-11
申请人： Sun-Mo An , Shin-Ho Chu
发明人： Sun-Mo An , Shin-Ho Chu
IPC分类号： H03K17/22 , H03K19/20
CPC分类号： G01R31/2879 , H01H85/0241 , H01H85/46 , H01H2085/466
摘要： A fuse circuit for a semiconductor integrated circuit includes a control unit configured to activate a fuse set control signal in response to an external command signal, and a plurality of fuse sets, each configured so that power is supplied to internal fuses in response to the activation of the fuse set control signal.
摘要翻译：一种用于半导体集成电路的熔丝电路包括：控制单元，被配置为响应于外部命令信号激活熔丝组控制信号，以及多个熔丝组，每个熔丝组被配置为响应于激活而向内部熔丝供电的熔丝组控制信号。

3. 发明申请

US20080101134A1 Self refresh control device 有权
标题翻译：自刷新控制装置
公开(公告)号：US20080101134A1
公开(公告)日：2008-05-01
申请号：US12000956
申请日：2007-12-19
申请人： Shin-Ho Chu
发明人： Shin-Ho Chu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/4074 , G11C2211/4068
摘要： Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes a first voltage supplying block for supplying a first voltage to the semiconductor memory device in response to an inputted control signal; and a second voltage supplying block for supplying a second voltage to the semiconductor memory device in response to the inputted control signal, wherein the first and the second voltages are used as a bulk voltage of a transistor included in the semiconductor memory device.
摘要翻译：这里公开了一种用于减少截止状态下的晶体管的电流泄漏的自刷新控制装置。用于控制半导体存储器件中使用的电压的装置包括：第一电压供应块，用于响应输入的控制信号向半导体存储器件提供第一电压; 以及第二电压供应块，用于响应于输入的控制信号向半导体存储器件提供第二电压，其中第一和第二电压被用作包括在半导体存储器件中的晶体管的体电压。

4. 发明授权

US07580310B2 Self refresh control device 有权
标题翻译：自刷新控制装置
公开(公告)号：US07580310B2
公开(公告)日：2009-08-25
申请号：US12000956
申请日：2007-12-19
申请人： Shin-Ho Chu
发明人： Shin-Ho Chu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/4074 , G11C2211/4068
摘要： Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes a first voltage supplying block for supplying a first voltage to the semiconductor memory device in response to an inputted control signal; and a second voltage supplying block for supplying a second voltage to the semiconductor memory device in response to the inputted control signal, wherein the first and the second voltages are used as a bulk voltage of a transistor included in the semiconductor memory device.
摘要翻译：这里公开了一种用于减少截止状态下的晶体管的电流泄漏的自刷新控制装置。用于控制半导体存储器件中使用的电压的装置包括：第一电压供应块，用于响应输入的控制信号向半导体存储器件提供第一电压; 以及第二电压供应块，用于响应于输入的控制信号向半导体存储器件提供第二电压，其中第一和第二电压被用作包括在半导体存储器件中的晶体管的体电压。

5. 发明授权

US08331170B2 Data transfer circuit, method thereof, and memory device including data transfer circuit 有权
标题翻译：数据传输电路及其方法，包括数据传输电路的存储器件
公开(公告)号：US08331170B2
公开(公告)日：2012-12-11
申请号：US12833796
申请日：2010-07-09
申请人： Shin-Ho Chu
发明人： Shin-Ho Chu
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1006 , G11C7/106 , G11C7/1066 , G11C7/1069 , H03K3/356139
摘要： A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and restore the pattern of the data before the pattern change.
摘要翻译：数据传输电路包括被配置为利用数据驱动第一行的第一驱动器，配置成改变通过第一行传输的数据的模式并产生模式改变的数据的模式改变单元，被配置为驱动第二行驱动器的第二驱动器符合模式变化的数据; 以及图案恢复单元，被配置为接收通过第二行传送的图案改变的数据，并且在图案改变之前恢复数据的图案。

6. 发明授权

US08045408B2 Semiconductor integrated circuit with multi test 失效
标题翻译：半导体集成电路多测试
公开(公告)号：US08045408B2
公开(公告)日：2011-10-25
申请号：US12363338
申请日：2009-01-30
申请人： Shin-Ho Chu , Jong-Won Lee
发明人： Shin-Ho Chu , Jong-Won Lee
IPC分类号： G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/18 , G11C2029/1202 , G11C2029/1204 , G11C2029/2602
摘要： A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.
摘要翻译：半导体集成电路包括：多模控制信号生成单元，被配置为根据多重测试来控制上/下按钮I / O开关控制信号的激活，其控制上/下垫中的I / O开关模式信号和读/写鉴别信号;多模式解码器，被配置为输出多个席选择信号，以根据多测试模式有效写入信号同时激活多个地址;以及矩阵控制器，被配置为使得字线和I / O开关根据上/下垫I / O开关控制信号和多功能选择信号。

7. 发明授权

US08000164B2 Self refresh operation of semiconductor memory device 有权
公开(公告)号：US08000164B2
公开(公告)日：2011-08-16
申请号：US12724394
申请日：2010-03-15
申请人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
发明人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/20 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C2211/4061
摘要： A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

8. 发明授权

US07710809B2 Self refresh operation of semiconductor memory device 有权
标题翻译：半导体存储器件的自刷新操作
公开(公告)号：US07710809B2
公开(公告)日：2010-05-04
申请号：US11786594
申请日：2007-04-12
申请人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
发明人： Jin-Hong Ahn , Bong-Hwa Jeong , Saeng-Hwan Kim , Shin-Ho Chu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/20 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C2211/4061
摘要： A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.
摘要翻译：一种用于驱动半导体存储器件的方法，包括初始化与单元阵列中包括的每个对应行的刷新时间对应的第一数据; 在进入自刷新模式之后存储对应于包括在第一行中的列数据的第二数据; 根据对于预定的刷新周期的基于对应的第一数据选择的刷新周期，在对单元阵列中的其他行执行刷新操作的同时，通过检测第一行的刷新时间来设置与第一行对应的第一数据，其中刷新在预定的刷新周期期间不对第一行执行操作; 将第二数据恢复到第一行; 并对其他行重复上述步骤，从而设置对应的第一数据，直到完成所有行的设置步骤或自刷新模式期满。

9. 发明授权

US07274619B2 Wordline enable circuit in semiconductor memory device and method thereof 有权
标题翻译：半导体存储器件中的字线使能电路及其方法
公开(公告)号：US07274619B2
公开(公告)日：2007-09-25
申请号：US11320967
申请日：2005-12-30
申请人： Jong-Won Lee , Shin-Ho Chu
发明人： Jong-Won Lee , Shin-Ho Chu
IPC分类号： G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C2211/4065
摘要： There is provided a wordline enable circuit and its method for reducing power consumption by controlling a wordline select signal in a self-refresh mode. The wordline enable circuit includes a wordline control signal generating unit for outputting an untoggled wordline control signal while a unit wordline block is enabled in a self-refresh mode; a wordline enable signal generating unit for generating a wordline enable control signal, controlled by the untoggled wordline control signal and a toggled address signal, and a first to an n-th wordline enable power supply signals; and a wordline block enable unit for enabling each wordline, controlled by the wordline enable control signal and the first to the n-th wordline enable power supply signals.
摘要翻译：提供了一种字线使能电路及其通过在自刷新模式中控制字线选择信号来降低功耗的方法。字线使能电路包括字线控制信号生成单元，用于在自刷新模式下启用单位字线块时输出未切换的字线控制信号; 字线使能信号生成单元，用于生成由未切换的字线控制信号和切换的地址信号控制的字线使能控制信号，以及第一至第n字线使能电源信号; 以及字线块使能单元，用于启用由字线使能控制信号和第一至第n字线使能电源信号控制的每个字线。

10. 发明授权

US06215710B1 Apparatus and method for controlling data strobe signal in DDR SDRAM 有权
标题翻译：在DDR SDRAM中控制数据选通信号的装置和方法
公开(公告)号：US06215710B1
公开(公告)日：2001-04-10
申请号：US09428535
申请日：1999-10-28
申请人： Jong-Hee Han , Shin-Ho Chu
发明人： Jong-Hee Han , Shin-Ho Chu
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1072
摘要： A method for controlling a data strobe signal having preamble and postamble sections in a double data rate (DDR) synchronous dynamic random access memory (SDRAM), wherein the preamble section is a low signal section of the data strobe signal one clock before data is issued and wherein the postamble section is a low signal section of the data strobe signal half clock before the data issue is complete in a data issue section, includes the steps of: controlling a high impedance status of the data strobe signal at sections, except for the data issue section, the preamble section and the postamble section, in response to a first control signal, wherein the high impedance status is related to a level between high and low signal levels; and controlling a point of time when the preamble section of the data strobe signal begins in response to a second control signal.
摘要翻译：一种用于在双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）中控制具有前导码和后同步码段的数据选通信号的方法，其中前导码部分是数据选通信号的低信号部分，并且其中所述后同步部分是在数据发布部分中数据发布完成之前数据选通信号半时钟的低信号部分，包括以下步骤：在部分控制数据选通信号的高阻抗状态，除了数据发布部分，前导码部分和后同步部分，响应于第一控制信号，其中高阻抗状态与高信号电平和低信号电平之间的电平相关; 以及控制数据选通信号的前导码部分响应于第二控制信号开始的时间点。

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