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1. 发明授权

US06215710B1 Apparatus and method for controlling data strobe signal in DDR SDRAM 有权
标题翻译：在DDR SDRAM中控制数据选通信号的装置和方法
公开(公告)号：US06215710B1
公开(公告)日：2001-04-10
申请号：US09428535
申请日：1999-10-28
申请人： Jong-Hee Han , Shin-Ho Chu
发明人： Jong-Hee Han , Shin-Ho Chu
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1072
摘要： A method for controlling a data strobe signal having preamble and postamble sections in a double data rate (DDR) synchronous dynamic random access memory (SDRAM), wherein the preamble section is a low signal section of the data strobe signal one clock before data is issued and wherein the postamble section is a low signal section of the data strobe signal half clock before the data issue is complete in a data issue section, includes the steps of: controlling a high impedance status of the data strobe signal at sections, except for the data issue section, the preamble section and the postamble section, in response to a first control signal, wherein the high impedance status is related to a level between high and low signal levels; and controlling a point of time when the preamble section of the data strobe signal begins in response to a second control signal.
摘要翻译：一种用于在双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）中控制具有前导码和后同步码段的数据选通信号的方法，其中前导码部分是数据选通信号的低信号部分，并且其中所述后同步部分是在数据发布部分中数据发布完成之前数据选通信号半时钟的低信号部分，包括以下步骤：在部分控制数据选通信号的高阻抗状态，除了数据发布部分，前导码部分和后同步部分，响应于第一控制信号，其中高阻抗状态与高信号电平和低信号电平之间的电平相关; 以及控制数据选通信号的前导码部分响应于第二控制信号开始的时间点。

2. 发明授权

US06392911B1 Reduced power bit line selection in memory circuits 有权
标题翻译：在存储器电路中减少功率位线选择
公开(公告)号：US06392911B1
公开(公告)日：2002-05-21
申请号：US09474872
申请日：1999-12-29
申请人： Jong-Hee Han
发明人： Jong-Hee Han
IPC分类号： G11C506
CPC分类号： G11C11/4094 , G11C7/06 , G11C7/12 , G11C11/4091
摘要： This invention relates to a method and apparatus for reducing power consumption during bit line selection in memory circuits. Two adjacent memory cell arrays in memory circuits generally share a row of bit-line sense amplifiers. These sense amplifiers are usually connected to a memory cell array via a number of switches. These switches specifically connect the bit lines of each of two adjacent memory cell arrays to the row of sense amplifiers. By controlling the switches, the row of sense amplifiers can be directed to serve either one of the two adjacent memory cell arrays. The switches may be connected to a bit line select control line. To achieve the desired reduction of power consumption, the present invention controls the bit-line select control line in such a way that the bit-line select control line connected to a currently active memory cell array is switched only when the next memory operation involves an adjacent memory cell array sharing the same row of bit-line sense amplifiers controlled by such bit line select control line.
摘要翻译：本发明涉及一种用于在存储器电路中减少位线选择期间的功耗的方法和装置。存储器电路中的两个相邻的存储单元阵列通常共享一行位线读出放大器。这些感测放大器通常通过多个开关连接到存储单元阵列。这些开关将两个相邻存储单元阵列中的每一个的位线专门连接到读出放大器行。通过控制开关，读出放大器行可以被引导以服务于两个相邻存储单元阵列中的任一个。开关可以连接到位线选择控制线。为了实现所需的功耗的降低，本发明控制位线选择控制线，使得只有当下一个存储器操作涉及一个存储器单元阵列时，连接到当前活动存储单元阵列的位线选择控制线才被切换共享由这种位线选择控制线控制的同一行位线读出放大器的相邻存储单元阵列。

3. 发明授权

US07117514B2 Multi-tuner television receiving apparatus and method of restricting the viewing 有权
标题翻译：多调谐器电视接收装置和限制观看的方法
公开(公告)号：US07117514B2
公开(公告)日：2006-10-03
申请号：US09780673
申请日：2001-02-12
申请人： Jong-Hee Han
发明人： Jong-Hee Han
IPC分类号： H04N7/16 , H04N5/74
CPC分类号： H04N5/50 , H04N21/4263 , H04N21/4532 , H04N21/4542
摘要： A process and network able to restrict a video appliance equipped with either a single tuner or with multiple tuners, from receiving and subsequently displaying video image signals represented by an accompanying broadcast discretionary control data to include a high level of objectional content. A multi-tuner television receiving appliance may be constructed with at least two tuners receiving a program; a viewing restricting portion detecting a discretionary control data of the program received through one of the tuners and blocking AGC signals of the tuner receiving the program when the discretionary control data is greater than a discretionary threshold; a control portion blocking AFT signals of the other tuners when the viewing of the program received the receiving tuner is restricted.
摘要翻译：能够限制配备有单个调谐器或多个调谐器的视频设备的处理和网络从接收和随后显示由伴随的广播自由控制数据表示的视频图像信号以包括高级别的异议内容。多调谐器电视接收设备可以构造成具有接收节目的至少两个调谐器; 观看限制部分，当所述自由控制数据大于任意阈值时，检测通过所述调谐器之一接收到的节目的任意控制数据并阻止接收所述节目的调谐器的AGC信号; 当接收到接收调谐器的节目的观看被限制时，控制部分阻止其他调谐器的AFT信号。

4. 发明授权

US06489822B2 Delay locked loop with delay control unit for noise elimination 有权
标题翻译：具有延迟控制单元的延迟锁定环，用于消除噪声
公开(公告)号：US06489822B2
公开(公告)日：2002-12-03
申请号：US09747886
申请日：2000-12-22
申请人： Jong-Hee Han
发明人： Jong-Hee Han
IPC分类号： H03L706
CPC分类号： G11C7/222 , G11C7/22 , H03L7/0814 , H03L7/089 , H03L7/093
摘要： Disclosed is a delay locked loop (DLL) for use in a semiconductor memory device, which has the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. The DLL includes a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal, a comparator for comparing the time-delayed signal from the modification block and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal, and a delay control unit for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the modification unit, if the counted value satisfies a predetermined condition.
摘要翻译：公开了一种用于半导体存储器件的延迟锁定环（DLL），其具有减少或消除电源噪声，随机噪声或其他不规则噪声的能力。该DLL包括可控延迟修改单元，用于延迟馈送到其中的时钟信号以产生时间延迟信号;比较器，用于比较来自修改块的时间延迟信号和参考信号;以及确定时间的加或减根据比较结果延迟以产生相应的输出信号;以及延迟控制单元，用于对相应的输出信号被激活的数量进行计数，并产生用于控制对修改单元的时间延迟的相加或减法的信号，如果计数值满足预定条件。

5. 发明授权

US06741506B2 Reduced power bit line selection in memory circuits 有权
标题翻译：在存储器电路中减少功率位线选择
公开(公告)号：US06741506B2
公开(公告)日：2004-05-25
申请号：US10424202
申请日：2003-04-25
申请人： Jong-Hee Han
发明人： Jong-Hee Han
IPC分类号： G11C700
CPC分类号： G11C11/4094 , G11C7/06 , G11C7/12 , G11C11/4091
摘要： A method for reducing power consumption during bit line selection in memory circuits is disclosed. According to an exemplary aspect of the method, two adjacent memory cell arrays in memory circuits generally share a row of bit-line sense amplifiers. These sense amplifiers are usually connected to a memory cell array via a number of switches. These switches specifically connect the bit lines of each of two adjacent memory cell arrays to the row of sense amplifiers. By controlling the switches, the row of sense amplifiers can be directed to serve either one of the two adjacent memory cell arrays. The switches may be connected to a bit line select control line. To achieve the desired reduction of power consumption, the present invention controls the bit-line select control line in such a way that the bit-line select control line connected to a currently active memory cell array is switched only when the next memory operation involves an adjacent memory cell array sharing the same row of bit-line sense amplifiers controlled by such bit line select control line.
摘要翻译：公开了一种用于在存储器电路中的位线选择期间降低功耗的方法。根据该方法的示例性方面，存储器电路中的两个相邻的存储单元阵列通常共享一行位线读出放大器。这些感测放大器通常通过多个开关连接到存储单元阵列。这些开关将两个相邻存储单元阵列中的每一个的位线专门连接到读出放大器行。通过控制开关，读出放大器行可以被引导以服务于两个相邻存储单元阵列中的任一个。开关可以连接到位线选择控制线。为了实现所需的功耗的降低，本发明控制位线选择控制线，使得只有当下一个存储器操作涉及一个存储器单元阵列时，连接到当前活动存储单元阵列的位线选择控制线才被切换共享由这种位线选择控制线控制的同一行位线读出放大器的相邻存储单元阵列。

6. 发明授权

US06538956B2 Semiconductor memory device for providing address access time and data access time at a high speed 有权
公开(公告)号：US06538956B2
公开(公告)日：2003-03-25
申请号：US09867811
申请日：2001-05-30
申请人： Je-Hun Ryu , Jong-Hee Han
发明人： Je-Hun Ryu , Jong-Hee Han
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4087
摘要： A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.

7. 发明授权

US06314050B1 Data strobe buffer in SDRAM 有权
标题翻译： SDRAM中的数据选通缓冲区
公开(公告)号：US06314050B1
公开(公告)日：2001-11-06
申请号：US09609323
申请日：2000-06-30
申请人： Seung-Hyun Yi , Jong-Hee Han
发明人： Seung-Hyun Yi , Jong-Hee Han
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1072 , G11C7/22
摘要： A data strobe buffer in SDRAM is disclosed. The data strobe buffer for a synchronous dynamic read only memory (SDRAM), comprising: a first dynamic buffer generating a first pulse at a rising edge of a data strobe signal; a second dynamic buffer generating a second pulse at a falling edge of the data strobe signal; and a block for generating an enable signal which is enabled in a range between a rising edge of an external clock signal and a logic high state of the second pulse, and providing the second dynamic buffer with the enable signal. The data strobe buffer ensures a minimum value of tDQSS parameter in DDR SDRAM even if speed of the chip increases or operation condition of the chip becomes tight, thereby preventing the data strobe buffer from being misoperated due to the damping and the fluctuation of the data strobe signal.
摘要翻译：公开了SDRAM中的数据选通缓冲器。用于同步动态只读存储器（SDRAM）的数据选通缓冲器，包括：第一动态缓冲器，在数据选通信号的上升沿产生第一脉冲; 第二动态缓冲器，在所述数据选通信号的下降沿产生第二脉冲; 以及用于产生使能信号的块，其在外部时钟信号的上升沿和第二脉冲的逻辑高状态之间的范围内被使能，并且向第二动态缓冲器提供使能信号。数据选通缓冲器确保DDR SDRAM中的tDQSS参数的最小值，即使芯片的速度增加或芯片的操作条件变得紧张，从而防止数据选通缓冲区由于阻尼和数据选通的波动而被误操作信号。

8. 发明授权

US06687169B2 Semiconductor memory device for providing address access time and data access time at a high speed 有权
标题翻译：用于以高速提供地址访问时间和数据访问时间的半导体存储器件
公开(公告)号：US06687169B2
公开(公告)日：2004-02-03
申请号：US10334610
申请日：2002-12-31
申请人： Je-Hun Ryu , Jong-Hee Han
发明人： Je-Hun Ryu , Jong-Hee Han
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4087
摘要： A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.
摘要翻译：通过与延迟锁定环（DLL）时钟同步地控制控制/地址块来提供用于执行高速地址访问和高速数据访问的半导体存储器件。半导体存储器件包括用于缓冲外部时钟的时钟缓冲器; 用于与外部时钟同步地生成DLL时钟的延迟锁定环（DLL）; 控制信号缓冲器，用于接收和缓冲外部控制信号以与DLL时钟同步地产生内部控制信号; 以及用于接收和缓冲外部地址信号以与DLL时钟同步地生成内部地址信号的地址缓冲器。

9. 发明授权

US06556488B2 Delay locked loop for use in semiconductor memory device 有权
标题翻译：延迟锁定环用于半导体存储器件
公开(公告)号：US06556488B2
公开(公告)日：2003-04-29
申请号：US09742816
申请日：2000-12-19
申请人： Jong-Hee Han
发明人： Jong-Hee Han
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , H03L7/0814 , H03L7/089 , H03L7/095 , H03L7/107
摘要： A delay locked loop is used in a semiconductor memory device. The delay locked loop includes a controllable delay chain block for controlling a delay time of a clock signal coupled thereto, a comparison block for detecting the increase and decrease in the delay time by comparing a reference clock signal with a delayed clock signal generated from the controllable delay chain block, and an instant locking delay control block for controlling the increase and decrease in the delay time of the delay chain block in response to an output signal of the comparison block, the delayed clock signal and the reference clock signal.
摘要翻译：在半导体存储器件中使用延迟锁定环。延迟锁定环路包括用于控制与其耦合的时钟信号的延迟时间的可控延迟链块，比较块，用于通过将参考时钟信号与从可控制的时钟信号产生的延迟时钟信号进行比较来检测延迟时间的增加和减少延迟链块和瞬时锁定延迟控制块，用于响应于比较块的输出信号，延迟的时钟信号和参考时钟信号来控制延迟链块的延迟时间的增加和减小。

10. 发明授权

US06243302B1 Apparatus for outputting data using common pull-up/pull-down lines with reduced load 有权
标题翻译：用于使用具有减小的负载的公共上拉/下拉线输出数据的装置
公开(公告)号：US06243302B1
公开(公告)日：2001-06-05
申请号：US09605306
申请日：2000-06-28
申请人： Min-Ho Yoon , Jong-Hee Han
发明人： Min-Ho Yoon , Jong-Hee Han
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C11/4093
摘要： A synchronous memory device includes: a plurality of pipelatch circuits storing data as pull-up and pull-down signals, transferring the stored data to pull-up and pull-down lines and producing initialization signals to initialize the pull-up and pull-down lines in response to a pipe count signal; common pull-up and pull-down lines coupled to the pull-up and pull-down lines in response to the pipe count signal and the initialization signals; initialization unit for supplying a power supply to the pull-up and pull-down lines in response to a reset signal, the pipe count signal and the initialization signals; an output buffer outputting the data transferred by the common pull-up and pull-down lines; and a precharging unit for precharging the pull-up and pull-down lines and the common pull-up and pull-down lines in response to an output signal from the output buffer, wherein the common pull-up and pull-down lines is precharged to a ground voltage level.
摘要翻译：同步存储装置包括：多个管线电路，其将数据存储为上拉和下拉信号，将存储的数据传送到上拉和下拉线，并产生初始化信号以初始化上拉和下拉响应于管道计数信号的线路; 响应于管道计数信号和初始化信号，耦合到上拉和下拉线路的公共上拉和下拉线路; 初始化单元，用于响应于复位信号，管道计数信号和初始化信号向上拉和下拉线路供电; 输出缓冲器，输出由公共上拉和下拉线传输的数据; 以及预充电单元，用于响应于来自所述输出缓冲器的输出信号对所述上拉和下拉线以及所述公共上拉线和下拉线进行预充电，其中所述公共上拉和下拉线被预充电到地电压级。

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