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1. 发明申请

US20060215475A1 Wordline enable circuit in semiconductor memory device and method thereof 有权
标题翻译：半导体存储器件中的字线使能电路及其方法
公开(公告)号：US20060215475A1
公开(公告)日：2006-09-28
申请号：US11320967
申请日：2005-12-30
申请人： Jong-Won Lee , Shin-Ho Chu
发明人： Jong-Won Lee , Shin-Ho Chu
IPC分类号： G11C7/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C2211/4065
摘要： There is provided a wordline enable circuit and its method for reducing power consumption by controlling a wordline select signal in a self-refresh mode. The wordline enable circuit includes a wordline control signal generating unit for outputting an untoggled wordline control signal while a unit wordline block is enabled in a self-refresh mode; a wordline enable signal generating unit for generating a wordline enable control signal, controlled by the untoggled wordline control signal and a toggled address signal, and a first to an n-th wordline enable power supply signals; and a wordline block enable unit for enabling each wordline, controlled by the wordline enable control signal and the first to the n-th wordline enable power supply signals.
摘要翻译：提供了一种字线使能电路及其通过在自刷新模式中控制字线选择信号来降低功耗的方法。字线使能电路包括字线控制信号生成单元，用于在自刷新模式下启用单位字线块时输出未切换的字线控制信号; 字线使能信号生成单元，用于生成由未切换的字线控制信号和切换的地址信号控制的字线使能控制信号，以及第一至第n字线使能电源信号; 以及字线块使能单元，用于启用由字线使能控制信号和第一至第n字线使能电源信号控制的每个字线。

2. 发明授权

US08045408B2 Semiconductor integrated circuit with multi test 失效
标题翻译：半导体集成电路多测试
公开(公告)号：US08045408B2
公开(公告)日：2011-10-25
申请号：US12363338
申请日：2009-01-30
申请人： Shin-Ho Chu , Jong-Won Lee
发明人： Shin-Ho Chu , Jong-Won Lee
IPC分类号： G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/18 , G11C2029/1202 , G11C2029/1204 , G11C2029/2602
摘要： A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.
摘要翻译：半导体集成电路包括：多模控制信号生成单元，被配置为根据多重测试来控制上/下按钮I / O开关控制信号的激活，其控制上/下垫中的I / O开关模式信号和读/写鉴别信号;多模式解码器，被配置为输出多个席选择信号，以根据多测试模式有效写入信号同时激活多个地址;以及矩阵控制器，被配置为使得字线和I / O开关根据上/下垫I / O开关控制信号和多功能选择信号。

3. 发明授权

US07274619B2 Wordline enable circuit in semiconductor memory device and method thereof 有权
标题翻译：半导体存储器件中的字线使能电路及其方法
公开(公告)号：US07274619B2
公开(公告)日：2007-09-25
申请号：US11320967
申请日：2005-12-30
申请人： Jong-Won Lee , Shin-Ho Chu
发明人： Jong-Won Lee , Shin-Ho Chu
IPC分类号： G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C2211/4065
摘要： There is provided a wordline enable circuit and its method for reducing power consumption by controlling a wordline select signal in a self-refresh mode. The wordline enable circuit includes a wordline control signal generating unit for outputting an untoggled wordline control signal while a unit wordline block is enabled in a self-refresh mode; a wordline enable signal generating unit for generating a wordline enable control signal, controlled by the untoggled wordline control signal and a toggled address signal, and a first to an n-th wordline enable power supply signals; and a wordline block enable unit for enabling each wordline, controlled by the wordline enable control signal and the first to the n-th wordline enable power supply signals.
摘要翻译：提供了一种字线使能电路及其通过在自刷新模式中控制字线选择信号来降低功耗的方法。字线使能电路包括字线控制信号生成单元，用于在自刷新模式下启用单位字线块时输出未切换的字线控制信号; 字线使能信号生成单元，用于生成由未切换的字线控制信号和切换的地址信号控制的字线使能控制信号，以及第一至第n字线使能电源信号; 以及字线块使能单元，用于启用由字线使能控制信号和第一至第n字线使能电源信号控制的每个字线。

4. 发明授权

US09061904B2 Cellulose sheathed nanotube fiber 有权
标题翻译：纤维素护套纳米管纤维
公开(公告)号：US09061904B2
公开(公告)日：2015-06-23
申请号：US13157758
申请日：2011-06-10
申请人： Minoru Miyauchi , Jianjun Miao , Trevor J. Simmons , Jong-Won Lee , Thomas V. Doherty , Jonathan S. Dordick , Robert J. Linhardt
发明人： Minoru Miyauchi , Jianjun Miao , Trevor J. Simmons , Jong-Won Lee , Thomas V. Doherty , Jonathan S. Dordick , Robert J. Linhardt
IPC分类号： B23B9/04 , B29C47/04 , D02G3/00 , B82Y30/00 , D01D5/00 , D01F1/09 , D01F8/02 , H01G9/02 , H01G11/52
CPC分类号： B82Y30/00 , D01D5/0007 , D01F1/09 , D01F2/02 , D01F8/02 , H01G9/02 , H01G11/52 , Y02E60/13 , Y10T428/2918
摘要： Embodiments of the invention provide a cellulose-sheathed carbon nanotube fiber. One aspect of the invention provides a sheathed nanotube fiber comprising: a carbon nanotube fiber; and a cellulose sheath extending co-axially along at least a first portion of a length of the carbon nanotube fiber. Another aspect of the invention provides a method of forming a sheathed carbon nanotube fiber, the method comprising: co-electrospinning a carbon nanotube fiber gel core within a cellulose solution sheath.
摘要翻译：本发明的实施方案提供了一种纤维素包覆的碳纳米管纤维。本发明的一个方面提供一种护套纳米管纤维，其包含：碳纳米管纤维; 以及沿所述碳纳米管纤维的长度的至少第一部分同轴延伸的纤维素护套。本发明的另一方面提供了一种形成护套碳纳米管纤维的方法，所述方法包括：在纤维素溶液鞘内共同静电纺丝碳纳米管纤维凝胶芯。

5. 发明申请

US20140063888A1 MEMORY ARRAY PLANE SELECT AND METHODS 有权
标题翻译：内存阵列选择和方法
公开(公告)号：US20140063888A1
公开(公告)日：2014-03-06
申请号：US13597520
申请日：2012-08-29
申请人： Jong-Won Lee , Gianpaolo Spadini
发明人： Jong-Won Lee , Gianpaolo Spadini
IPC分类号： G11C5/06 , H01L21/8239 , G11C11/00
CPC分类号： G11C13/0023 , G11C5/025 , G11C8/12 , G11C11/1653 , G11C11/1659 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71
摘要： Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.
摘要翻译：提供了存储器阵列及其形成方法。示例性存储器阵列可以包括具有以矩阵形式布置的多个存储单元和多个平面选择装置的至少一个平面。多个存储器单元的组通信地耦合到多个平面选择装置中的相应一个。具有元件的解码逻辑形成在衬底材料中并且通信地耦合到多个平面选择装置。多个存储单元和多个平面选择装置不形成在基板材料中。

6. 发明授权

US08298088B2 Method and system for operating online 8-direction battle game using personal computer 有权
标题翻译：使用个人电脑进行在线8方向战斗游戏的方法和系统
公开(公告)号：US08298088B2
公开(公告)日：2012-10-30
申请号：US12760722
申请日：2010-04-15
申请人： Jong-Won Lee
发明人： Jong-Won Lee
IPC分类号： A63F13/12
CPC分类号： A63F13/422 , A63F13/833 , A63F2300/407 , A63F2300/6054 , A63F2300/8029
摘要： A method and system for operating an online 8-direction battle game using a personal computer (PC) are provided. The system operates the 8-direction battle game through interfacing with a game providing module to provide the 8-direction battle game in an online mode with a PC. The system includes an auto-targeting unit to automatically target an object to perform a battle against a character designated by a user of the PC in the 8-direction battle game, the object being within a predetermined range from a position of the character, and a game controller to automatically control a direction in which the character faces the object based on a distance between the object and the character.
摘要翻译：提供了一种使用个人计算机（PC）操作在线8方向战斗游戏的方法和系统。该系统通过与游戏提供模块的接口操作8方向战斗游戏，以PC在线模式提供8方向战斗游戏。该系统包括自动定位单元，用于自动对象，以在与8个方向的战斗游戏中的PC的用户指定的角色进行对抗，该对象位于从角色位置的预定范围内，以及游戏控制器，用于基于对象和角色之间的距离来自动控制角色面向对象的方向。

7. 发明授权

US08199600B2 Voltage generator for peripheral circuit 有权
标题翻译：外围电路用电压发生器
公开(公告)号：US08199600B2
公开(公告)日：2012-06-12
申请号：US11529421
申请日：2006-09-27
申请人： Ho-Uk Song , Jong-Won Lee
发明人： Ho-Uk Song , Jong-Won Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A voltage generator for a peripheral circuit, the voltage generator includes: a voltage supplier supplying a peripheral circuit voltage having a voltage level maintained at a reference voltage level, the peripheral circuit voltage outputted in response to a driving signal; and a voltage level compensator increasing the voltage level of the peripheral circuit voltage in response to a column path command.
摘要翻译：一种用于外围电路的电压发生器，所述电压发生器包括：提供具有保持在参考电压电平的电压电平的外围电路电压的电压供给器，响应于驱动信号输出的外围电路电压; 以及电压电平补偿器，其响应于列路径命令增加外围电路电压的电压电平。

8. 发明申请

US20110305903A1 SHEATHED NANOTUBE FIBER AND METHOD OF FORMING SAME 有权
公开(公告)号：US20110305903A1
公开(公告)日：2011-12-15
申请号：US13157758
申请日：2011-06-10
申请人： Minoru Miyauchi , Jianjun Miao , Trevor J. Simmons , Jong-Won Lee , Thomas V. Doherty , Jonathan S. Dordick , Robert J. Linhardt
发明人： Minoru Miyauchi , Jianjun Miao , Trevor J. Simmons , Jong-Won Lee , Thomas V. Doherty , Jonathan S. Dordick , Robert J. Linhardt
IPC分类号： B32B9/04 , B29C47/04 , D02G3/00 , B82Y30/00
CPC分类号： B82Y30/00 , D01D5/0007 , D01F1/09 , D01F2/02 , D01F8/02 , H01G9/02 , H01G11/52 , Y02E60/13 , Y10T428/2918
摘要： Embodiments of the invention provide a cellulose-sheathed carbon nanotube fiber. One aspect of the invention provides a sheathed nanotube fiber comprising: a carbon nanotube fiber; and a cellulose sheath extending co-axially along at least a first portion of a length of the carbon nanotube fiber. Another aspect of the invention provides a method of forming a sheathed carbon nanotube fiber, the method comprising: co-electrospinning a carbon nanotube fiber gel core within a cellulose solution sheath.
摘要翻译：本发明的实施方案提供了一种纤维素包覆的碳纳米管纤维。本发明的一个方面提供一种护套纳米管纤维，其包含：碳纳米管纤维; 以及沿所述碳纳米管纤维的长度的至少第一部分同轴延伸的纤维素护套。本发明的另一方面提供了一种形成护套碳纳米管纤维的方法，所述方法包括：在纤维素溶液鞘内共同静电纺丝碳纳米管纤维凝胶芯。

9. 发明申请

US20100015729A1 METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME 失效
标题翻译：形成薄膜层的方法和制造包括其的半导体器件的方法
公开(公告)号：US20100015729A1
公开(公告)日：2010-01-21
申请号：US12503440
申请日：2009-07-15
申请人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
发明人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
IPC分类号： H01L21/28
CPC分类号： H01L27/11507 , H01L21/3105 , H01L21/31053 , H01L28/55
摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.
摘要翻译：在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

10. 发明申请

US20070264793A1 Methods of Manufacturing Semiconductor Memory Devices with Unit Cells Having Charge Trapping Layers 失效
标题翻译：制造具有电荷陷阱层的单元电池的半导体存储器件的方法
公开(公告)号：US20070264793A1
公开(公告)日：2007-11-15
申请号：US11746761
申请日：2007-05-10
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwam Shim , Jong-Won Lee
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwam Shim , Jong-Won Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/11568
摘要： In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.
摘要翻译：在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。形成从衬底突出的隔离层以填充沟槽。在基板上形成第一层之后，在第一层上形成预备的第二层图案。预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。在初步第二层和隔离层上形成第三层。在第三层上形成第四层。部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

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