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    • 1. 发明授权
    • Loadport bridge for semiconductor fabrication tools
    • 用于半导体制造工具的承载桥
    • US08944739B2
    • 2015-02-03
    • US13486024
    • 2012-06-01
    • Shih-Hung ChenYing XiaoChin-Hsiang Lin
    • Shih-Hung ChenYing XiaoChin-Hsiang Lin
    • H01L21/677
    • H01L21/6773H01L21/67733H01L21/67775
    • A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.
    • 一种具有用于在半导体制造工具之间传输晶片的装置的晶片处理系统。 在一个实施例中,该装置是装载端口机构,其包括具有第一和第二安装端的外壳,每个端部处的对接端口被构造和尺寸设计成与半导体工具的承载端口相接合,以及至少一个可运输的晶片传送机械手 在对接端口之间的晶片。 晶片传送机器人在第一和第二工具的载荷端口移动或接收来自工具机器人的晶片。 桥接机构允许一个或多个晶片在不同工具的载荷端口之间单独传输,而不依赖于FAB的自动化材料处理系统(AMHS),用于在诸如FOUP或其它晶片载体之间的体晶片传输。
    • 6. 发明申请
    • Multi-zone EPD Detectors
    • 多区域EPD探测器
    • US20130157387A1
    • 2013-06-20
    • US13328172
    • 2011-12-16
    • Chien-An ChenYen-Shuo SuYing XiaoChin-Hsiang Lin
    • Chien-An ChenYen-Shuo SuYing XiaoChin-Hsiang Lin
    • H01L21/66H01L21/306
    • H01J37/32963H01J37/3299H01L21/31116
    • The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities.
    • 本公开涉及具有多区域端点检测系统的半导体本体蚀刻装置。 在一些实施例中,多区域终点检测系统具有容纳根据蚀刻工艺被蚀刻的工件的处理室。 多个端点检测器(EPD)探针位于处理室内。 相应的EPD探针位于处理室中的不同区域内,从而能够检测来自处理室内的多个区域的终点信号。 检测到的终点信号从多个EPD探针提供给高级处理控制(APC)单元。 APC单元被配置为基于检测到的终点信号对调谐旋钮进行蚀刻工艺参数调整,从而考虑蚀刻非均匀性。
    • 9. 发明申请
    • Plasma Etcher Design with Effective No-Damage In-Situ Ash
    • 等离子体蚀刻设计,有效无损原位灰
    • US20130160795A1
    • 2013-06-27
    • US13337418
    • 2011-12-27
    • Ying XiaoChin-Hsiang Lin
    • Ying XiaoChin-Hsiang Lin
    • H01L21/3065B08B6/00
    • H01J37/321G03F7/427H01J37/32596H01J37/32706H01J37/32807H01J37/32889H01J37/32899H01L21/31138
    • In some embodiments, the present disclosure relates to a plasma etching system having direct and localized plasma sources in communication with a processing chamber. The direct plasma is operated to provide a direct plasma to the processing chamber for etching a semiconductor workpiece. The direct plasma has a high potential, formed by applying a large bias voltage to the workpiece. After etching is completed the bias voltage and direct plasma source are turned off. The localized plasma source is then operated to provide a low potential, localized plasma to a position within the processing chamber that is spatially separated from the workpiece. The spatial separation results in formation of a diffused plasma having a zero/low potential that is in contact with the workpiece. The zero/low potential of the diffused plasma allows for reactive ashing to be performed, while mitigating workpiece damage resulting from ion bombardment caused by positive plasma potentials.
    • 在一些实施例中,本公开涉及具有与处理室连通的直接和局部等离子体源的等离子体蚀刻系统。 操作直接等离子体以向处理室提供直接等离子体以蚀刻半导体工件。 直接等离子体具有高电位,通过向工件施加大的偏置电压而形成。 蚀刻完成后,偏置电压和直接等离子体源关闭。 然后操作局部等离子体源以将低电位局部等离子体提供到处理室内与工件空间分离的位置。 空间分离导致形成具有与工件接触的零/低电位的扩散等离子体。 扩散等离子体的零/低电位允许执行反应性灰化,同时减轻由正等离子体电位引起的离子轰击造成的工件损伤。