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1. 发明授权

US06770138B2 Pattern for monitoring epitaxial layer washout 失效
标题翻译：用于监测外延层冲洗的图案
公开(公告)号：US06770138B2
公开(公告)日：2004-08-03
申请号：US10047379
申请日：2002-01-14
申请人： Shih-Feng Huang , Chih-Feng Huang , Kuo-Su Huang
发明人： Shih-Feng Huang , Chih-Feng Huang , Kuo-Su Huang
IPC分类号： C30B3500
CPC分类号： H01L23/544 , C30B33/00 , H01L2924/0002 , Y10T117/1004 , H01L2924/00
摘要： A pattern for monitoring epitaxial layer washout is disclosed. The pattern includes first and second sub-patterns. The first sub-pattern has a shape and defines one or more minimum dimensions. Obfuscation of the first sub-pattern means that epitaxial washout has occurred at least for dimensions equal to or less than the minimum dimensions. The second sub-pattern has the same shape of the first sub-pattern, but defines one or more maximum dimensions. Obfuscation of the second sub-pattern means that epitaxial washout has occurred for dimensions equal to or less than the maximum dimensions. The sub-patterns can include a pair of separated features, such as a pair of interlocking but separated L-shaped features, the separation of which defines the dimensions of the sub-patterns.
摘要翻译：公开了一种用于监测外延层冲洗的图案。该模式包括第一和第二子模式。第一子图案具有形状并且定义一个或多个最小尺寸。第一子图案的混淆意味着至少在尺寸等于或小于最小尺寸的情况下发生外延冲洗。第二子图案具有与第一子图案相同的形状，但是定义一个或多个最大尺寸。第二子图案的混淆意味着对于等于或小于最大尺寸的尺寸发生外延冲洗。子图案可以包括一对分离的特征，例如一对互锁但分开的L形特征，其分离限定子图案的尺寸。

2. 发明授权

US06580131B2 LDMOS device with double N-layering and process for its manufacture 有权
标题翻译： LDMOS器件具有双层N层及其制造工艺
公开(公告)号：US06580131B2
公开(公告)日：2003-06-17
申请号：US10266712
申请日：2002-10-08
申请人： Chih-Feng Huang , Kuo-Su Huang
发明人： Chih-Feng Huang , Kuo-Su Huang
IPC分类号： H01L21336
CPC分类号： H01L29/66681 , H01L29/0847 , H01L29/66674 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N−regions instead of the single epitaxial N−region that is used by devices of the prior art. The resistivities and thicknesses of these two N−regions are chosen so that their mean resistivity is similar to that of the aforementioned single N−layer. A key feature is that the lower N−layer (i.e. the one closest to the P−substrate) has a resistivity that is greater than that of the upper N−layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on-resistance. A process for manufacturing the device is also described.
摘要翻译：通过具有两个外延N区而不是由现有技术的器件使用的单个外延N区来改善LDMOS器件的击穿电压和导通电阻之间的折衷。选择这两个N区的电阻率和厚度，使得它们的平均电阻率类似于上述单个N层的平均电阻率。一个关键特征是下层N层（即最接近P型衬底的层）的电阻率大于上层N层的电阻率。如果满足这些约束，如说明书中更详细描述的那样，可以实现高达60％的击穿电压的改善，而不必增加导通电阻。还描述了用于制造该装置的方法。

3. 发明授权

US06475870B1 P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture 有权
标题翻译： P型LDMOS器件采用埋层解决穿孔问题及其制造工艺
公开(公告)号：US06475870B1
公开(公告)日：2002-11-05
申请号：US09910158
申请日：2001-07-23
申请人： Chih-Feng Huang , Kuo-Su Huang
发明人： Chih-Feng Huang , Kuo-Su Huang
IPC分类号： H01L21331
CPC分类号： H01L29/1083 , H01L29/42368 , H01L29/7835
摘要： P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.
摘要翻译： P型LDMOS器件难以与N型LDMOS器件集成而不增加额外的掩模，因为前者由于早期穿通而无法实现与后者相同的击穿电压。通过在N衬底外延沉积到P-衬底上的附加工艺步骤之前已经克服了这个问题，其中通过离子注入在衬底的表面上形成掩埋的N +层。当电压施加到漏极时，该N +掩埋层显着地减小了从P-阱向外延伸的耗尽层的宽度，从而基本上提高穿通电压。

4. 发明授权

US06348371B1 Method of forming self-aligned twin wells 有权
标题翻译：形成自对准双孔的方法
公开(公告)号：US06348371B1
公开(公告)日：2002-02-19
申请号：US09809831
申请日：2001-03-19
申请人： Chih-Feng Huang , Kuo-Su Huang , Shun-Liang Hsu
发明人： Chih-Feng Huang , Kuo-Su Huang , Shun-Liang Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823892
摘要： A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate. A subsequent anneal procedure results in the formation of a N well region, in the first portion of the semiconductor substrate, self-aligned to the formed P well region, located in the second portion of the semiconductor substrate.
摘要翻译：已经开发了用于为CMOS器件形成自对准双阱区而不使用氧化阻滞氮化硅层的工艺。使用第一离子注入程序将N型离子放置在半导体衬底的第一部分中，随后进行湿热氧化过程，导致在N型离子上生长厚二氧化硅层，在第一部分半导体衬底，同时在轻掺杂的P型半导体衬底的第二部分上生长薄的二氧化硅层。第二离子注入程序使P型离子通过薄二氧化硅层进入半导体衬底的第二部分，而厚二氧化硅层防止P型离子到达半导体衬底的第一部分。随后的退火程序导致在位于半导体衬底的第二部分中的形成的P阱区自对准的半导体衬底的第一部分中的N阱区的形成。

5. 发明授权

US06770951B2 P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture 有权
标题翻译： P型LDMOS器件采用埋层解决穿孔问题及其制造工艺
公开(公告)号：US06770951B2
公开(公告)日：2004-08-03
申请号：US10266731
申请日：2002-10-08
申请人： Chih-Feng Huang , Kuo-Su Huang
发明人： Chih-Feng Huang , Kuo-Su Huang
IPC分类号： H01L2900
CPC分类号： H01L29/1083 , H01L29/42368 , H01L29/7835
摘要： P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.
摘要翻译： P型LDMOS器件难以与N型LDMOS器件集成而不增加额外的掩模，因为前者由于早期穿通而无法实现与后者相同的击穿电压。通过在N衬底外延沉积到P-衬底上的附加工艺步骤之前已经克服了这个问题，其中通过离子注入在衬底的表面上形成掩埋的N +层。当电压施加到漏极时，该N +掩埋层显着地减小了从P-阱向外延伸的耗尽层的宽度，从而基本上提高穿通电压。

6. 发明授权

US06486034B1 Method of forming LDMOS device with double N-layering 有权
标题翻译：用双层N层形成LDMOS器件的方法
公开(公告)号：US06486034B1
公开(公告)日：2002-11-26
申请号：US09908824
申请日：2001-07-20
申请人： Chih-Feng Huang , Kuo-Su Huang
发明人： Chih-Feng Huang , Kuo-Su Huang
IPC分类号： H01L21336
CPC分类号： H01L29/66681 , H01L29/0847 , H01L29/66674 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N− regions instead of the single epitaxial N− region that is used by devices of the prior art. The resistivities and thicknesses of these two N− regions are chosen so that their mean resistivity is similar to that of the aforementioned single N− layer. A key feature is that the lower N− layer (i.e. the one closest to the P− substrate) has a resistivity that is greater than that of the upper N− layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on resistance. A process for manufacturing the device is also described.
摘要翻译：通过具有两个外延N-区域而不是由现有技术的器件使用的单个外延N-区域来改善LDMOS器件的击穿电压和导通电阻之间的折衷。选择这两个N-区域的电阻率和厚度，使得它们的平均电阻率类似于上述单个N-层的平均电阻率。一个关键的特征是下层N-层（即最靠近P-衬底的层）具有大于上层N层的电阻率。如果满足这些约束，如说明书中更详细描述的那样，可以实现高达60％的击穿电压的改善，而不必增加导通电阻。还描述了用于制造该装置的方法。

7. 发明授权

US08710544B2 Isolated SCR ESD device 失效
标题翻译：隔离式SCR ESD器件
公开(公告)号：US08710544B2
公开(公告)日：2014-04-29
申请号：US13345694
申请日：2012-01-07
申请人： Chih-Feng Huang
发明人： Chih-Feng Huang
IPC分类号： H01L29/73
CPC分类号： H01L27/0262 , H01L29/7436
摘要： The present invention discloses an isolated SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a first high density doped region located in the first well and having a second conductivity type; a second well nearby the first well and having the second conductivity type; a second high density doped region located in the second well and having the second conductivity type; and a third high density doped region located in the second well and having the first conductivity type, wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad.
摘要翻译：本发明公开了一种隔离型SCR ESD器件，包括：衬底; 位于衬底中的第一阱，其浮置并具有第一导电类型; 位于第一阱中并具有第二导电类型的第一高密度掺杂区; 第二井靠近第一井，具有第二导电类型; 位于第二阱中并具有第二导电类型的第二高密度掺杂区; 以及位于所述第二阱中并且具有所述第一导电类型的第三高密度掺杂区域，其中所述第一高密度掺杂区域用于与焊盘电连接，并且其中所述第一阱不具有高密度掺杂区域，所述高密度掺杂区域具有用于与垫连接的第一导电类型。

8. 发明授权

US08492801B2 Semiconductor structure with high breakdown voltage and resistance 有权
标题翻译：半导体结构具有高击穿电压和电阻
公开(公告)号：US08492801B2
公开(公告)日：2013-07-23
申请号：US11798206
申请日：2007-05-11
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/66
CPC分类号： H01L28/20
摘要： A semiconductor structure with high breakdown voltage and high resistance and method for manufacturing the same. The semiconductor structure at least comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; two first wells having the first conductive type and formed within the deep well; a second well having the first conductive type and formed between the two first wells within the deep well, and an implant dosage of the second well lighter than an implant dosage of each of the two first wells; and two first doping regions having the first conductive type and respectively formed within the two first wells.
摘要翻译：具有高击穿电压和高电阻的半导体结构及其制造方法。半导体结构至少包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型并形成在深井内的两个第一阱; 具有第一导电类型并形成在深井内的两个第一阱之间的第二阱，以及比两个第一孔中的每一个的植入物剂量轻的第二阱的植入剂量; 和具有第一导电类型并分别形成在两个第一阱内的两个第一掺杂区域。

9. 发明授权

US08258752B2 Integrated PMOS transistor and Schottky diode and charging switch circuit employing the integrated device 有权
标题翻译：集成PMOS晶体管和肖特基二极管和充电开关电路采用集成器件
公开(公告)号：US08258752B2
公开(公告)日：2012-09-04
申请号：US12629956
申请日：2009-12-03
申请人： Kuo-Chin Chiu , Chih-Feng Huang
发明人： Kuo-Chin Chiu , Chih-Feng Huang
IPC分类号： H02J7/00 , H02J7/04 , H02J7/16
CPC分类号： H03K17/063 , H01L27/0727 , H02J7/0031 , H03K2217/0036 , Y10T279/26
摘要： The present invention discloses an integrated PMOS transistor and Schottky diode, comprising a PMOS transistor which includes a gate, a source, a drain and a channel region between the source and drain, wherein the source, drain and channel region are formed in a substrate, and a parasitic diode is formed between the drain and the channel region; and a Schottky diode formed in the substrate and connected in reverse series with the parasitic diode, the Schottky diode having one end connected with the parasitic diode and the other end connected with the source.
摘要翻译：本发明公开了一种集成PMOS晶体管和肖特基二极管，其包括PMOS晶体管，PMOS晶体管在源极和漏极之间包括栅极，源极，漏极和沟道区域，其中源极，漏极和沟道区域形成在衬底中，并且在漏极和沟道区域之间形成寄生二极管; 和形成在衬底中并与寄生二极管反向串联连接的肖特基二极管，肖特基二极管的一端与寄生二极管连接，另一端与源极连接。

10. 发明授权

US07858466B2 Different-voltage device manufactured by a CMOS compatible process and high-voltage device used in the different-voltage device 有权
标题翻译：由CMOS兼容工艺制造的不同电压器件和用于不同电压器件的高压器件
公开(公告)号：US07858466B2
公开(公告)日：2010-12-28
申请号：US11682621
申请日：2007-03-06
申请人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
发明人： Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823892
摘要： A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
摘要翻译：一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。通过调制离子掺杂分布来调整击穿电压。此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

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