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1. 发明授权

US08503144B2 Control circuit with protection circuit for power supply 有权
标题翻译：具有电源保护电路的控制电路
公开(公告)号：US08503144B2
公开(公告)日：2013-08-06
申请号：US12338112
申请日：2008-12-18
申请人： Meng-Jen Tsai , Chao-Chih Lin , Rui-Hong Lu , Chiu-Chih Chiang
发明人： Meng-Jen Tsai , Chao-Chih Lin , Rui-Hong Lu , Chiu-Chih Chiang
IPC分类号： H02H3/20
CPC分类号： H02H7/1213 , H02M1/32 , H02M3/33507
摘要： A control circuit with protection circuit for power supply according to the present invention comprises a peak-detection circuit and a protection circuit. The peak-detection circuit detects an AC input voltage and generates a peak-detection signal. The protection circuit generates a reset signal to reduce the output of the power supply in response to the peak-detection signal. The present invention can protect the power supply in response to the AC input voltage effectively through the peak-detection circuit.
摘要翻译：根据本发明的具有电源保护电路的控制电路包括峰值检测电路和保护电路。峰值检测电路检测交流输入电压并产生峰值检测信号。保护电路产生复位信号，以响应峰值检测信号减小电源的输出。本发明可以通过峰值检测电路有效地响应于AC输入电压来保护电源。

2. 发明授权

US07888704B2 Semiconductor device for electrostatic discharge protection 有权
标题翻译：用于静电放电保护的半导体器件
公开(公告)号：US07888704B2
公开(公告)日：2011-02-15
申请号：US12222746
申请日：2008-08-15
申请人： Chiu-Chih Chiang , Han-Chung Tai
发明人： Chiu-Chih Chiang , Han-Chung Tai
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly.
摘要翻译：公开了一种用于静电放电保护的半导体器件，并且至少包括高压寄生器可控硅整流器（HVSCR）和二极管。 HVSCR具有阳极和阴极，HVSCR的阴极耦合到地面。串联连接到HVSCR的二极管也具有阳极和阴极。二极管的阳极耦合到HVSCR的阳极，二极管的阴极耦合到施加正电压的端子。二极管具有第二导电类型区域，其可以构造成形成彼此间隔开的几个条或小块。这些小块可以是任何形状，并定期或随机排列。

3. 发明申请

US20100038677A1 Semiconductor device for electrostatic discharge protection 有权
标题翻译：用于静电放电保护的半导体器件
公开(公告)号：US20100038677A1
公开(公告)日：2010-02-18
申请号：US12222746
申请日：2008-08-15
申请人： Chiu-Chih Chiang , Han-Chung Tai
发明人： Chiu-Chih Chiang , Han-Chung Tai
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly.
摘要翻译：公开了一种用于静电放电保护的半导体器件，并且至少包括高压寄生器可控硅整流器（HVSCR）和二极管。 HVSCR具有阳极和阴极，并且HVSCR的阴极耦合到地面。串联连接到HVSCR的二极管也具有阳极和阴极。二极管的阳极耦合到HVSCR的阳极，二极管的阴极耦合到施加正电压的端子。二极管具有第二导电类型区域，其可以构造成形成彼此间隔开的几个条或小块。这些小块可以是任何形状，并定期或随机排列。

4. 发明授权

US07615976B2 Switching circuit of power converter having voltage-clipping device to improve efficiency 有权
标题翻译：具有电压钳位装置的功率转换器的开关电路，以提高效率
公开(公告)号：US07615976B2
公开(公告)日：2009-11-10
申请号：US11407537
申请日：2006-04-19
申请人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Wei-Hsuan Huang , Ta-yung Yang
发明人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Wei-Hsuan Huang , Ta-yung Yang
IPC分类号： G05F1/00
CPC分类号： H02M1/36 , H02M2001/0006
摘要： A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.
摘要翻译：提出了一种电源转换器的开关电路。它包括电压限幅装置，电阻装置，第一晶体管和第二晶体管。电压限幅装置耦合到输入电压。第一晶体管与用于切换输入电压的电压限幅装置串联连接。第二晶体管被耦合以响应于控制信号来控制第一晶体管和电压限幅装置。当第二晶体管截止时，电阻器件提供偏置电压以接通压限器件和第一晶体管。一旦第二晶体管导通，第一晶体管被截止并且电压限幅器件被负偏置。钳位装置被开发以钳位第一晶体管的最大电压。

5. 发明授权

US07589393B2 Semiconductor structure of a high side driver for two high voltage nodes with partially linked deep wells and method for manufacturing the same 有权
标题翻译：具有部分连接的深井的两个高压节点的高侧驱动器的半导体结构及其制造方法
公开(公告)号：US07589393B2
公开(公告)日：2009-09-15
申请号：US11492039
申请日：2006-07-25
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/06
CPC分类号： H01L29/10 , H01L29/063 , H01L29/7835
摘要： A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate, a first deep well and a second deep well, a first heavy ion-doped region and a second heavy ion-doped region. The first deep well and second deep well are formed in the substrate, which are separated but partially linked with each other, and the first deep well and the second deep well have the same ion-doped type. The first heavy ion-doped region is formed in the first deep well for connecting to a first high voltage, and the first heavy ion-doped region has the same ion-doped type as the first deep well. The second heavy ion-doped region is formed in the second deep well for connecting to a second high voltage, and the second heavy ion-doped region has the same ion-doped type as the first deep well.
摘要翻译：高侧驱动器的半导体结构包括离子掺杂结。离子掺杂结包括衬底，第一深阱和第二深阱，第一重离子掺杂区和第二重离子掺杂区。第一深阱和第二深阱形成在衬底中，其被分离但部分地彼此连接，并且第一深阱和第二深阱具有相同的离子掺杂型。第一重离子掺杂区域形成在第一深阱中以连接到第一高电压，并且第一重离子掺杂区域具有与第一深阱相同的离子掺杂类型。第二重离子掺杂区域形成在第二深阱中用于连接到第二高电压，并且第二重离子掺杂区域具有与第一深阱相同的离子掺杂类型。

6. 发明申请

US20080017926A1 Semiconductor structure of a high side driver and method for manufacturing the same 有权
标题翻译：高侧驱动器的半导体结构及其制造方法
公开(公告)号：US20080017926A1
公开(公告)日：2008-01-24
申请号：US11489558
申请日：2006-07-20
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L21/765 , H01L24/48 , H01L27/0805 , H01L29/0847 , H01L29/7835 , H01L2224/48091 , H01L2924/00014 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate and a deep well. The deep well is formed in the substrate and has a first concave structure. The ion-doped junction includes a semiconductor region connected to the first concave structure of the deep well and having substantially the same ion-doping concentration as the substrate.
摘要翻译：高侧驱动器的半导体结构包括离子掺杂结。离子掺杂结包括衬底和深阱。深孔形成在基板中并具有第一凹形结构。离子掺杂结包括连接到深阱的第一凹陷结构并且具有与衬底基本上相同的离子掺杂浓度的半导体区域。

7. 发明申请

US20070290276A1 VOLTAGE-CLIPPING DEVICE WITH HIGH BREAKDOWN VOLTAGE 有权
标题翻译：具有高断路电压的电压切断装置
公开(公告)号：US20070290276A1
公开(公告)日：2007-12-20
申请号：US11424530
申请日：2006-06-15
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/94
CPC分类号： H01L29/808
摘要： The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.
摘要翻译：本发明提出了利用由两个耗尽边界形成的夹断机构的电压剪切装置。可以响应于栅极电压来调节电压限幅装置的限幅电压; 准连接井的缺口; 以及准连接阱的掺杂浓度和深度以及与准连接阱具有互补掺杂极性的阱。与传统的变压器相比，电压钳位装置可以与微型尺寸的电压降压装置集成在半导体器件内。

8. 发明申请

US20070290261A1 SELF-DRIVEN LDMOS TRANSISTOR 审中-公开
标题翻译：自激式LDMOS晶体管
公开(公告)号：US20070290261A1
公开(公告)日：2007-12-20
申请号：US11424532
申请日：2006-06-15
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/861
摘要： The present invention provides a self-driven LDMOS, which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal will be clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS will be turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention doesn't lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential doesn't vary in response to an increment of the drain-voltage potential.
摘要翻译：本发明提供一种自驱动LDMOS，其利用漏极端子和辅助区域之间的寄生电阻器。寄生电阻形成在准连接深N型阱中的两个耗尽边界之间。当两个耗尽边界夹闭时，栅极端子处的栅极电压电位将在所述漏极端子处的漏极电压电位处被钳位。由于栅极电压电位被设计为等于或高于启动阈值电压，所以LDMOS将被相应地导通。此外，不需要额外的管芯空间和掩模工艺来制造寄生电阻器。此外，本发明的寄生电阻器不降低LDMOS的击穿电压和操作速度。此外，当两个耗尽边界夹断时，栅极电压电位不随着漏极 - 电压电位的增加而变化。

9. 发明授权

US08558349B2 Integrated circuit for a high-side transistor driver 有权
标题翻译：集成电路用于高端晶体管驱动器
公开(公告)号：US08558349B2
公开(公告)日：2013-10-15
申请号：US11464075
申请日：2006-08-11
申请人： Chiu-Chih Chiang , Chih-Feng Huang , Ta-yung Yang
发明人： Chiu-Chih Chiang , Chih-Feng Huang , Ta-yung Yang
IPC分类号： H01L21/70
CPC分类号： H01L27/0629
摘要： The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well serve as the isolation structures. The low voltage control circuit is located outside the deep N well and the floating circuit is located inside the deep N well. The deep N well forms a high voltage junction barrier for isolating the control circuit from the floating circuit.
摘要翻译：公开了高压集成电路。高压集成电路包括低压控制电路，浮置电路，P衬底，设置在衬底中的深N阱以及设置在P衬底中的多个P阱。 P井和深N井作为隔离结构。低压控制电路位于深N阱外部，浮动电路位于深N阱内。深N阱形成用于将控制电路与浮置电路隔离的高压结屏障。

10. 发明申请

US20120217657A1 MULTI-CHIP MODULE PACKAGE 审中-公开
标题翻译：多芯片模块包装
公开(公告)号：US20120217657A1
公开(公告)日：2012-08-30
申请号：US13468862
申请日：2012-05-10
申请人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Lih-Ming Doong
发明人： Chih-Feng Huang , Chiu-Chih Chiang , You-Kuo Wu , Lih-Ming Doong
IPC分类号： H01L23/488
CPC分类号： H01L25/18 , H01L23/3107 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/072 , H01L25/074 , H01L2224/05639 , H01L2224/29101 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/73265 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.
摘要翻译：提供了一种多芯片模块封装，其包括经由第一导电粘合剂安装并电连接到第一芯片载体的第一芯片，经由第二导电粘合剂安装的第二芯片，并电连接到第二芯片载体，第二芯片载体是与第一芯片载体间隔开，其中第二导电粘合剂由与第一导电材料相同的粘合剂材料制成，多个导电元件将第一芯片电连接到第二芯片，以及密封剂封装第一芯片芯片，第一芯片载体，第二芯片，第二芯片载体和多个导电元件，允许两个芯片载体的一部分暴露于密封剂，使得第一芯片和第二芯片能够由分离第一和第二芯片载体。

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