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1. 发明授权

US5324969A High-breakdown voltage field-effect transistor 失效
标题翻译：高击穿电压场效应晶体管
公开(公告)号：US5324969A
公开(公告)日：1994-06-28
申请号：US930189
申请日：1992-08-12
申请人： Shigeyuki Murai , Takayoshi Higashino , Masao Nishida
发明人： Shigeyuki Murai , Takayoshi Higashino , Masao Nishida
IPC分类号： H01L21/285 , H01L21/338 , H01L29/10 , H01L29/812 , H01L29/80 , H01L29/161 , H01L29/167
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/1029 , H01L29/812
摘要： A field-effect transistor including a first channel layer, formed in contacting relationship with a gate electrode, and a second channel layer, formed on one side or both sides of the first channel layer in non-contacting relationship with the gate electrode, the carrier concentration in the second channel layer being higher than that in the first channel layer but lower than that in high-impurity concentration active layers forming drain and source regions. The field-effect transistor employs an offset gate configuration in which the gate electrode is formed in contacting relationship with the first channel layer at a position nearer to the high-impurity concentration active layer forming the source region than to the high-impurity concentration active layer forming the drain region. A dummy gate is formed and ion implantation is performed from two different angles using the dummy gate as a mask, thereby efficiently forming the source region, drain region, and second channel layer in a sequence of successive processing steps. By combining the suitably patterned first and second ion shielding layers, the gate to source electrode spacing and the gate to drain electrode spacing are controlled by the accuracy to which the second ion shielding layer can be formed.
摘要翻译：一种场效应晶体管，包括与栅电极形成为接触关系的第一沟道层和形成在与栅电极非接触关系的第一沟道层的一侧或两侧上的第二沟道层，载体第二沟道层中的浓度高于第一沟道层中的浓度，但低于形成漏极和源极区的高杂质浓度有源层中的浓度。场效应晶体管采用偏移栅极配置，其中栅极形成在与形成源极区更接近高杂质浓度有源层的位置处的第一沟道层的接触关系高于高杂质浓度有源层形成漏区。形成虚拟栅极，并使用伪栅极作为掩模从两个不同的角度进行离子注入，从而以连续的处理步骤的顺序有效地形成源极区域，漏极区域和第二沟道层。通过组合适当图案化的第一离子屏蔽层和第二离子屏蔽层，通过可以形成第二离子屏蔽层的精度来控制栅极 - 源极电极间距和栅 - 漏电极间距。

2. 发明授权

US5614814A Negative voltage genarating circuit 失效
标题翻译：负电压传感电路
公开(公告)号：US5614814A
公开(公告)日：1997-03-25
申请号：US365462
申请日：1994-12-28
申请人： Masao Nishida , Takayoshi Higashino , Yasoo Harada
发明人： Masao Nishida , Takayoshi Higashino , Yasoo Harada
IPC分类号： H02M3/07 , H02M3/18
CPC分类号： H02M3/07
摘要： A negative voltage generating circuit includes an oscillating unit constructed of a ring oscillator for outputting a pulse signal with a high frequency and a polarity inverting unit in which the pulse signal is inputted to charge negative voltage. This negative voltage generating circuit is miniaturized and outputs a stable negative voltage. Further, the negative voltage to be outputted can be controlled by varying a resistance value through a control of an FET in a voltage controlling unit.
摘要翻译：负电压产生电路包括由环形振荡器构成的振荡单元，用于输出高频脉冲信号和极性反转单元，其中输入脉冲信号以对负电压进行充电。该负电压发生电路小型化并输出稳定的负电压。此外，可以通过电压控制单元中的FET的控制来改变电阻值来控制要输出的负电压。

3. 发明授权

US06793435B2 Binder 失效
标题翻译：粘合剂
公开(公告)号：US06793435B2
公开(公告)日：2004-09-21
申请号：US10083414
申请日：2002-02-27
申请人： Takayoshi Higashino , Kizuku Kitada
发明人： Takayoshi Higashino , Kizuku Kitada
IPC分类号： B42F1302
CPC分类号： B42F13/06
摘要： A binder (10) has a base (14) having passages (14A, 14A) through which binding legs (13,13) can be inserted. The base (14) has a plurality of base-forming members (17,17) that can move relative to each other along the longitudinal direction. Each of the base-forming members (17,17) has first and second operating portions (22,23) that move when the base-forming members (17,17) are moved relative to each other. The second operating portions (23,23) move away from each other and press the binding legs (13,13) onto their binding positions when the first operating portions (22,22) are moved toward each other. The binding legs (13,13) are released and the first operating portions (22,22) move away from each other when the second operating portions (23,23) are moved toward each other.
摘要翻译：粘合剂（10）具有基部（14），该基部具有可插入结合腿（13,13）的通道（14A，14A）。基部（14）具有可沿着纵向方向相对于彼此移动的多个基座形成构件（17,17）。每个基座形成构件（17,17）具有当基座形成构件（17,17）相对于彼此移动时移动的第一和第二操作部分（22,23）。当第一操作部分（22,22）朝向彼此移动时，第二操作部分（23,23）彼此远离并且将绑定腿部（13,13）按压到其装订位置。当第二操作部分（23,23）朝向彼此移动时，绑定腿部（13,13）被释放并且第一操作部分（22,22）彼此远离。

4. 发明授权

US06739783B2 Binder 失效
标题翻译：粘合剂
公开(公告)号：US06739783B2
公开(公告)日：2004-05-25
申请号：US09884144
申请日：2001-06-20
申请人： Takayoshi Higashino , Seiichi Koike , Kenichi Izumi
发明人： Takayoshi Higashino , Seiichi Koike , Kenichi Izumi
IPC分类号： B42F300
CPC分类号： B42F9/00 , Y10T24/20 , Y10T24/203 , Y10T24/204 , Y10T24/206 , Y10T24/44436 , Y10T24/4453
摘要： A binder comprises an operating member supported on a base, a pressing member movable toward and away from the base by the movement of the operating member, and locking means for locking the operating member when the pressing member is set in a binding position. The operating member has a first operating spot and a second operating spot, and the operating member is locked to hold the pressing member at the binding position when the first operating spot is pressed toward the surface of the base, and unlocked to move the pressing member away from the base when the second operating spot is operated similarly.
摘要翻译：夹具包括支撑在基座上的操作构件，通过操作构件的移动可朝向和远离基座移动的按压构件;以及当按压构件被设置在装订位置时用于锁定操作构件的锁定装置。操作构件具有第一操作点和第二操作点，并且当第一操作点被压向基座的表面时，操作构件被锁定以将按压构件保持在装订位置，并且解锁以使按压构件当第二操作点的操作类似时，远离基座。

5. 发明授权

US5557141A Method of doping, semiconductor device, and method of fabricating semiconductor device 失效
标题翻译：掺杂方法，半导体器件和制造半导体器件的方法
公开(公告)号：US5557141A
公开(公告)日：1996-09-17
申请号：US220542
申请日：1994-03-30
申请人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
发明人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
IPC分类号： H01L21/18 , H01L21/22 , H01L21/225 , H01L21/285 , H01L21/314 , H01L21/324 , H01L21/329 , H01L21/335 , H01L21/338 , H01L21/8252 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/775 , H01L29/778 , H01L29/812 , H01L29/8605 , H01L23/58 , H01L29/00 , H01L29/06 , H01L31/0328
CPC分类号： B82Y10/00 , H01L21/22 , H01L21/2258 , H01L21/28587 , H01L21/28593 , H01L21/3144 , H01L21/3245 , H01L21/8252 , H01L27/0605 , H01L29/0891 , H01L29/1025 , H01L29/66075 , H01L29/66196 , H01L29/66462 , H01L29/66469 , H01L29/66856 , H01L29/66871 , H01L29/66878 , H01L29/66977 , H01L29/775 , H01L29/7787 , H01L29/812 , H01L29/8122 , H01L29/8605 , Y10S148/034 , Y10S438/962
摘要： A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.
摘要翻译：在III-V族化合物半导体的晶体上形成掺杂有杂质的III-V族化合物半导体的晶体，具有SiO x的未掺杂膜和防止V族原子扩散的膜（例如SiN膜） SiO x膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。

6. 发明授权

US5350709A Method of doping a group III-V compound semiconductor 失效
标题翻译：掺杂III-V族化合物半导体的方法
公开(公告)号：US5350709A
公开(公告)日：1994-09-27
申请号：US75232
申请日：1993-06-10
申请人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
发明人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
IPC分类号： H01L21/18 , H01L21/22 , H01L21/225 , H01L21/285 , H01L21/314 , H01L21/324 , H01L21/329 , H01L21/335 , H01L21/338 , H01L21/8252 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/775 , H01L29/778 , H01L29/812 , H01L29/8605
CPC分类号： B82Y10/00 , H01L21/22 , H01L21/2258 , H01L21/28587 , H01L21/28593 , H01L21/3144 , H01L21/3245 , H01L21/8252 , H01L27/0605 , H01L29/0891 , H01L29/1025 , H01L29/66075 , H01L29/66196 , H01L29/66462 , H01L29/66469 , H01L29/66856 , H01L29/66871 , H01L29/66878 , H01L29/66977 , H01L29/775 , H01L29/7787 , H01L29/812 , H01L29/8122 , H01L29/8605 , Y10S148/034 , Y10S438/962
摘要： A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.
摘要翻译：掺杂III-V族化合物半导体与杂质的方法，其中在未掺杂的SiOx膜和用于防止V族原子扩散的膜（例如，SiN膜）之后，依次形成在组的晶体上 III-V族化合物半导体，对该样品进行至少一次热处理以使SiOx膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。使用这种掺杂层形成方法，制造场效应晶体管，二极管，电阻层，二维电子气或一维量子线，零维量子箱，电子波干涉装置等。

7. 发明授权

US06873828B2 Compound semiconductor switching device for high frequency switching 有权
标题翻译：用于高频开关的复合半导体开关器件
公开(公告)号：US06873828B2
公开(公告)日：2005-03-29
申请号：US09855030
申请日：2001-05-15
申请人： Tetsuro Asano , Takayoshi Higashino , Koichi Hirata
发明人： Tetsuro Asano , Takayoshi Higashino , Koichi Hirata
IPC分类号： H01L21/338 , H01L21/8232 , H01L27/06 , H01L29/812 , H01P1/15 , H03K17/00 , H03K17/041 , H03K17/693 , H04B1/44
CPC分类号： H01L29/812 , H01L27/0605 , H03K17/04106 , H03K17/693
摘要： A compound semiconductor switching device is based on a designing guideline that isolation should be assured by reducing the gate width of switching FET, thereby reducing the capacitance of the FET. Proper isolation between the two signal passes IS obtained with a FET gate width of about 700 μm or smaller at a signal frequency of about 2.4 GHz or higher, without employing a shunt FET.
摘要翻译：复合半导体开关器件基于设计指南，通过减小开关FET的栅极宽度来确保隔离，从而降低FET的电容。在大约2.4GHz或更高的信号频率下，以大约700μm或更小的FET栅极宽度获得两个信号通路IS之间的适当隔离，而不使用分流FET。

8. 发明授权

US06867115B2 Compound semiconductor device 有权
标题翻译：复合半导体器件
公开(公告)号：US06867115B2
公开(公告)日：2005-03-15
申请号：US10211311
申请日：2002-08-05
申请人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
IPC分类号： H01L21/8252 , H01L27/06 , H01L21/265
CPC分类号： H01L24/05 , H01L21/8252 , H01L24/06 , H01L24/45 , H01L24/48 , H01L27/0605 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48644 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01031 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 μm for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 μm or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 μm or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.
摘要翻译：由于栅极宽度需要较大以达到低插入损耗，因此传统的化合物半导体开关器件容易具有大的芯片尺寸，并且连接焊盘和电路布线之间的间隔需要大于20μm以获得适当的他们之间的隔离。总体芯片尺寸减小，首先，通过减少在2.4GHz以上频率工作的开关FET的栅极宽度与省略分路FET一起减少到700μm或更小，然后通过减小连接焊盘之间的间隔并且电路布线为20mum以下。通过在连接焊盘的最外部分和衬底之间引入绝缘膜和杂质区域，可以实现分离的这种减少，以防止耗尽层的延伸。该装置的制造方法不需要用于容纳上述结构的任何额外的处理步骤，并且能够制造具有常规装置的五分之一尺寸的装置。

9. 发明授权

US06580107B2 Compound semiconductor device with depletion layer stop region 有权
标题翻译：具有耗尽层停止区域的复合半导体器件
公开(公告)号：US06580107B2
公开(公告)日：2003-06-17
申请号：US09973197
申请日：2001-10-10
申请人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
IPC分类号： H01L2980
CPC分类号： H01L24/05 , H01L21/8252 , H01L24/06 , H01L24/45 , H01L24/48 , H01L27/0605 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48644 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01031 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.
摘要翻译：由于栅极宽度需要较大以达到低插入损耗，因此传统的化合物半导体开关器件容易具有大的芯片尺寸，并且连接焊盘和电路布线之间的间隔需要大于20μm以获得适当的他们之间的隔离。总体芯片尺寸减小，首先，通过减少在2.4GHz以上频率工作的开关FET的栅极宽度与省略分路FET一起减少到700μm或更小，然后通过减小连接焊盘之间的间隔并且电路布线为20mum以下。通过在连接焊盘的最外部分和衬底之间引入绝缘膜和杂质区域，可以实现分离的这种减少，以防止耗尽层的延伸。该装置的制造方法不需要用于容纳上述结构的任何额外的处理步骤，并且能够制造具有常规装置的五分之一尺寸的装置。

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