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1. 发明申请

US20060006434A1 Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same 有权
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容的半导体器件及其制造方法
公开(公告)号：US20060006434A1
公开(公告)日：2006-01-12
申请号：US11220583
申请日：2005-09-08
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

2. 发明申请

US20060267105A1 Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same 审中-公开
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容的半导体器件及其制造方法
公开(公告)号：US20060267105A1
公开(公告)日：2006-11-30
申请号：US11493828
申请日：2006-07-27
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： A semiconductor device includes a semiconductor substrate, an insulated gate type transistor formed in the semiconductor substrate, and an insulated gate type capacitor formed in the semiconductor substrate. The insulated gate type transistor includes a gate insulating film of the transistor selectively formed on the semiconductor substrate, a gate electrode of the transistor formed on the gate insulating film of the transistor, and source-drain regions formed to interpose a body region of the transistor provided under the gate electrode of the transistor in a surface of the semiconductor substrate. The insulated gate type capacitor includes a gate insulating film of the capacitor selectively formed on the semiconductor substrate, a gate electrode of the capacitor formed on the gate insulating film of the capacitor, and extraction electrode regions formed to interpose a body region of the capacitor provided under the gate electrode of the capacitor in the surface of the semiconductor substrate. The extraction electrode regions have a common potential. The insulated gate type transistor has pocket regions of the transistor of a reverse conductivity type to that of the source-drain regions formed from the source-drain regions to a part of the body region of the transistor, the insulated gate type capacitor has no region of a reverse conductivity type to that of the extraction electrode regions in a vicinal region of the extraction electrode regions in the body region side of the capacitor, and the body region of the capacitor and the extraction electrode regions are formed to have different conductivity types from each other.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底中的绝缘栅型晶体管和形成在半导体衬底中的绝缘栅型电容器。绝缘栅型晶体管包括选择性地形成在半导体衬底上的晶体管的栅极绝缘膜，形成在晶体管的栅极绝缘膜上的晶体管的栅极电极以及形成为将晶体管的体区域插入的源极 - 漏极区域设置在半导体衬底的表面中的晶体管的栅电极下方。绝缘栅型电容器包括选择性地形成在半导体衬底上的电容器的栅极绝缘膜，形成在电容器的栅极绝缘膜上的电容器的栅电极，以及形成为插入电容器的体区的引出电极区域在半导体衬底表面的电容器的栅电极下方。引出电极区域具有共同的电位。绝缘栅型晶体管具有反向导电型晶体管的凹陷区域，其与由源极 - 漏极区域至晶体管的体区域的一部分形成的源极 - 漏极区域的凹槽区域，绝缘栅极型电容器没有区域与电容器的体区区域的引出电极区域的连续区域中的引出电极区域的反向导电类型相反，并且电容器和引出电极区域的体区形成为具有不同的导电类型彼此。

3. 发明授权

US07456464B2 Semiconductor device including insulated gate type transistor and insulated gate type variable capacitance, and method of manufacturing the same 失效
标题翻译：包括绝缘栅型晶体管和绝缘栅型可变电容的半导体器件及其制造方法
公开(公告)号：US07456464B2
公开(公告)日：2008-11-25
申请号：US11621177
申请日：2007-01-09
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P−pocket regions 17 and N−pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P−pocket regions 17 and the N−pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

4. 发明申请

US20070108494A1 SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE TYPE TRANSISTOR AND INSULATED GATE TYPE CAPACITANCE, AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容器的半导体器件及其制造方法
公开(公告)号：US20070108494A1
公开(公告)日：2007-05-17
申请号：US11621177
申请日：2007-01-09
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

5. 发明授权

US07176515B2 Semiconductor device including insulated gate type transistor and insulated gate type capacitance having protruded portions 有权
标题翻译：包括绝缘栅型晶体管和具有突出部分的绝缘栅型电容器的半导体器件
公开(公告)号：US07176515B2
公开(公告)日：2007-02-13
申请号：US11220583
申请日：2005-09-08
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

6. 发明授权

US07157765B2 Semiconductor device including insulated gate type transistor with pocket regions and insulated gate type capacitor with no region of reverse conductivity type 有权
标题翻译：半导体器件包括具有凹穴区的绝缘栅型晶体管和没有反向导电类型区域的绝缘栅型电容器
公开(公告)号：US07157765B2
公开(公告)日：2007-01-02
申请号：US10200523
申请日：2002-07-23
申请人： Shigenobu Maeda , Hiroyuki Takashiho , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashiho , Toshihide Oka
IPC分类号： H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P31 pocket regions 17 and N31 pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P31 pocket regions 17 and the N31 pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 31口袋区域17和N 31，分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于P 31口袋区域17和N 31区域27的引出电极区域相邻的反向导电型区域。

7. 发明授权

US07148726B2 Digital signal buffer circuit 失效
标题翻译：数字信号缓冲电路
公开(公告)号：US07148726B2
公开(公告)日：2006-12-12
申请号：US10961203
申请日：2004-10-12
申请人： Toshihide Oka , Hironobu Ito
发明人： Toshihide Oka , Hironobu Ito
IPC分类号： H03K19/094 , H03H11/76
CPC分类号： H04L25/0288
摘要： A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.
摘要翻译：延迟电路设置有多个不同尺寸的均衡晶体管，多个具有不同电阻值的均衡电阻器，具有差电容值的多个均衡电容器和开关电路。开关电路用于从均衡晶体管，均衡电阻器和均衡电容器中进行选择，以便调整数字反相信号的幅度电平和延迟量。

8. 发明申请

US20060232309A1 Digital-control-type phase-composing circuit system 失效
标题翻译：数字控制型组合电路系统
公开(公告)号：US20060232309A1
公开(公告)日：2006-10-19
申请号：US11305037
申请日：2005-12-19
申请人： Toshihide Oka
发明人： Toshihide Oka
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
摘要： A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as the control signal.
摘要翻译：数字控制相位合成电路系统具有相位合成电路，该相位合成电路被提供有两个具有相位差的输入时钟信号和一个控制信号，并且其组成输出时钟信号，该输出时钟信号具有两个输入的相位之间的相位基于通过控制信号的加权的时钟信号;二进制比较电路，其将输出时钟信号的相位与参考时钟信号的相位进行比较;第一上/下计数器，其对第一计数值进行递增或递减，由二进制相位比较电路进行比较的结果的基础，输出第一计数值的最高有效位，并且当在第一计数值中进行进位或借位时输出时钟脉冲，并且输出第二上/下计数器其基于作为操作时钟的时钟脉冲操作，基于第一计数值的最高有效位来增加或减少第二计数值，并输出th e第二计数值作为控制信号。

9. 发明授权

US07212049B2 Digital-control-type phase-composing circuit system 失效
标题翻译：数字控制型组合电路系统
公开(公告)号：US07212049B2
公开(公告)日：2007-05-01
申请号：US11305037
申请日：2005-12-19
申请人： Toshihide Oka
发明人： Toshihide Oka
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
摘要： A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as the control signal.
摘要翻译：数字控制相位合成电路系统具有相位合成电路，该相位合成电路被提供有两个具有相位差的输入时钟信号和一个控制信号，并且其组成输出时钟信号，该输出时钟信号具有两个输入的相位之间的相位基于通过控制信号的加权的时钟信号;二进制比较电路，其将输出时钟信号的相位与参考时钟信号的相位进行比较;第一上/下计数器，其对第一计数值进行递增或递减，由二进制相位比较电路进行比较的结果的基础，输出第一计数值的最高有效位，并且当在第一计数值中进行进位或借位时输出时钟脉冲，并且输出第二上/下计数器其基于作为操作时钟的时钟脉冲操作，基于第一计数值的最高有效位来增加或减少第二计数值，并输出th e第二计数值作为控制信号。

10. 发明授权

US08008972B2 Differential signal generator circuit 失效
标题翻译：差分信号发生器电路
公开(公告)号：US08008972B2
公开(公告)日：2011-08-30
申请号：US11934826
申请日：2007-11-05
申请人： Toshihide Oka , Masaaki Shimada
发明人： Toshihide Oka , Masaaki Shimada
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F3/45475 , H03F2200/78 , H03F2203/45101 , H03F2203/45586
摘要： A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage. The threshold voltage is adjusted in response to drain voltage of the second transistor.
摘要翻译：差分信号发生器电路包括：第一放大器，用于将输入信号与阈值电压进行比较并输出差分信号; 以及第二放大器，用于响应于差分信号调整阈值电压。第二放大器包括：第一晶体管和形成差分对的第二晶体管，每个晶体管的栅极接收相应的一个差分信号; 第三晶体管和第四晶体管，形成电流镜，所述第三晶体管连接在所述第一晶体管的漏极和参考电位点之间，所述第四晶体管连接在所述第二晶体管的漏极与所述参考电位之间; 连接到第一和第二晶体管的源极的电流源; 以及用于响应于外部施加的电流或电压来调节第一晶体管的漏极电流的调整部分。响应于第二晶体管的漏极电压来调整阈值电压。

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