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1. 发明授权

US06661040B2 Semiconductor device with insulating gate surrounded by impurity layers 有权
标题翻译：具有由杂质层包围的绝缘栅的半导体器件
公开(公告)号：US06661040B2
公开(公告)日：2003-12-09
申请号：US10137289
申请日：2002-05-03
申请人： Hiroyuki Takashino
发明人： Hiroyuki Takashino
IPC分类号： H01L2710
CPC分类号： H01L27/11568 , H01L27/0207 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A plurality of ONO films are provided in a matrix on a substrate surface. Gate electrodes are provided on each of the ONO films. Further provided in the substrate surface are n-type impurity layers and p-type impurity layers. Each of the p-type impurity layers is arranged between the n-type impurity layers. In a plan view of the substrate surface, the n-type impurity layers and the p-type impurity layers are arranged to surround the respective ONO films and the gate electrodes.
摘要翻译：在基板表面上的矩阵中设置多个ONO膜。在每个ONO膜上设置栅电极。在衬底表面中还设置有n型杂质层和p型杂质层。各p型杂质层配置在n型杂质层之间。在衬底表面的平面图中，n型杂质层和p型杂质层被布置成围绕各个ONO膜和栅电极。

2. 发明申请

US20060006434A1 Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same 有权
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容的半导体器件及其制造方法
公开(公告)号：US20060006434A1
公开(公告)日：2006-01-12
申请号：US11220583
申请日：2005-09-08
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

3. 发明申请

US20060267105A1 Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same 审中-公开
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容的半导体器件及其制造方法
公开(公告)号：US20060267105A1
公开(公告)日：2006-11-30
申请号：US11493828
申请日：2006-07-27
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： A semiconductor device includes a semiconductor substrate, an insulated gate type transistor formed in the semiconductor substrate, and an insulated gate type capacitor formed in the semiconductor substrate. The insulated gate type transistor includes a gate insulating film of the transistor selectively formed on the semiconductor substrate, a gate electrode of the transistor formed on the gate insulating film of the transistor, and source-drain regions formed to interpose a body region of the transistor provided under the gate electrode of the transistor in a surface of the semiconductor substrate. The insulated gate type capacitor includes a gate insulating film of the capacitor selectively formed on the semiconductor substrate, a gate electrode of the capacitor formed on the gate insulating film of the capacitor, and extraction electrode regions formed to interpose a body region of the capacitor provided under the gate electrode of the capacitor in the surface of the semiconductor substrate. The extraction electrode regions have a common potential. The insulated gate type transistor has pocket regions of the transistor of a reverse conductivity type to that of the source-drain regions formed from the source-drain regions to a part of the body region of the transistor, the insulated gate type capacitor has no region of a reverse conductivity type to that of the extraction electrode regions in a vicinal region of the extraction electrode regions in the body region side of the capacitor, and the body region of the capacitor and the extraction electrode regions are formed to have different conductivity types from each other.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底中的绝缘栅型晶体管和形成在半导体衬底中的绝缘栅型电容器。绝缘栅型晶体管包括选择性地形成在半导体衬底上的晶体管的栅极绝缘膜，形成在晶体管的栅极绝缘膜上的晶体管的栅极电极以及形成为将晶体管的体区域插入的源极 - 漏极区域设置在半导体衬底的表面中的晶体管的栅电极下方。绝缘栅型电容器包括选择性地形成在半导体衬底上的电容器的栅极绝缘膜，形成在电容器的栅极绝缘膜上的电容器的栅电极，以及形成为插入电容器的体区的引出电极区域在半导体衬底表面的电容器的栅电极下方。引出电极区域具有共同的电位。绝缘栅型晶体管具有反向导电型晶体管的凹陷区域，其与由源极 - 漏极区域至晶体管的体区域的一部分形成的源极 - 漏极区域的凹槽区域，绝缘栅极型电容器没有区域与电容器的体区区域的引出电极区域的连续区域中的引出电极区域的反向导电类型相反，并且电容器和引出电极区域的体区形成为具有不同的导电类型彼此。

4. 发明授权

US07456464B2 Semiconductor device including insulated gate type transistor and insulated gate type variable capacitance, and method of manufacturing the same 失效
标题翻译：包括绝缘栅型晶体管和绝缘栅型可变电容的半导体器件及其制造方法
公开(公告)号：US07456464B2
公开(公告)日：2008-11-25
申请号：US11621177
申请日：2007-01-09
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P−pocket regions 17 and N−pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P−pocket regions 17 and the N−pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

5. 发明申请

US20070108494A1 SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE TYPE TRANSISTOR AND INSULATED GATE TYPE CAPACITANCE, AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容器的半导体器件及其制造方法
公开(公告)号：US20070108494A1
公开(公告)日：2007-05-17
申请号：US11621177
申请日：2007-01-09
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

6. 发明授权

US07176515B2 Semiconductor device including insulated gate type transistor and insulated gate type capacitance having protruded portions 有权
标题翻译：包括绝缘栅型晶体管和具有突出部分的绝缘栅型电容器的半导体器件
公开(公告)号：US07176515B2
公开(公告)日：2007-02-13
申请号：US11220583
申请日：2005-09-08
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

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