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1. 发明申请

US20050151565A1 Digital signal buffer circuit 失效
标题翻译：数字信号缓冲电路
公开(公告)号：US20050151565A1
公开(公告)日：2005-07-14
申请号：US10961203
申请日：2004-10-12
申请人： Toshihide Oka , Hironobu Ito
发明人： Toshihide Oka , Hironobu Ito
IPC分类号： H03K5/13 , H03K19/0175 , H03K19/094 , H04B3/04 , H04L25/02 , H04L25/03
CPC分类号： H04L25/0288
摘要： A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.
摘要翻译：延迟电路设置有多个不同尺寸的均衡晶体管，多个具有不同电阻值的均衡电阻器，具有差电容值的多个均衡电容器和开关电路。开关电路用于从均衡晶体管，均衡电阻器和均衡电容器中进行选择，以便调整数字反相信号的幅度电平和延迟量。

2. 发明授权

US07148726B2 Digital signal buffer circuit 失效
标题翻译：数字信号缓冲电路
公开(公告)号：US07148726B2
公开(公告)日：2006-12-12
申请号：US10961203
申请日：2004-10-12
申请人： Toshihide Oka , Hironobu Ito
发明人： Toshihide Oka , Hironobu Ito
IPC分类号： H03K19/094 , H03H11/76
CPC分类号： H04L25/0288
摘要： A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.
摘要翻译：延迟电路设置有多个不同尺寸的均衡晶体管，多个具有不同电阻值的均衡电阻器，具有差电容值的多个均衡电容器和开关电路。开关电路用于从均衡晶体管，均衡电阻器和均衡电容器中进行选择，以便调整数字反相信号的幅度电平和延迟量。

3. 发明授权

US5494543A Process for producing vibrator for piezoelectric motor 失效
标题翻译：制造压电电动机振动器的方法
公开(公告)号：US5494543A
公开(公告)日：1996-02-27
申请号：US049156
申请日：1993-04-19
申请人： Hiroshi Okano , Hironobu Ito , Masao Kasuga
发明人： Hiroshi Okano , Hironobu Ito , Masao Kasuga
IPC分类号： H02N2/00 , H01L41/09 , B44C1/22
CPC分类号： H01L41/0906 , H01L41/257 , H01L41/332
摘要： A vibrator for a piezoelectric motor is produced by forming an elastic material into a predetermined shape, forming a piezoelectric material on the shaped elastic material for polarization and for driving, forming an electrode for polarization on the piezoelectric material, forming an electrode for driving on the surface of the electrode for polarization or on the piezoelectric material after stripping the electrode for polarization, and etching the elastic material into a predetermined shape has an elastic body and to remove the elastic body from a base. Instead of forming the piezoelectric material on the shaped elastic material for polarization and for driving, an electrode both for polarization and for driving can be formed on one face of the shaped elastic material, and the piezoelectric material can be formed on that electrode.
摘要翻译：通过将弹性材料形成为预定的形状，在成形的弹性材料上形成用于偏振和驱动的压电材料，在压电材料上形成用于极化的电极，形成用于驱动的电极用于极化的电极的表面或剥离用于极化的电极的压电材料的表面，并且将弹性材料蚀刻成预定的形状具有弹性体并且从基体去除弹性体。代替在用于偏振和驱动的成形弹性材料上形成压电材料，可以在成形弹性材料的一个面上形成用于偏振和驱动的电极，并且可以在该电极上形成压电材料。

4. 发明授权

US5052722A Intermediate coupler for hoses 失效
标题翻译：中间人联系人
公开(公告)号：US5052722A
公开(公告)日：1991-10-01
申请号：US515522
申请日：1990-04-30
申请人： Hiroshi Kubo , Hironobu Ito
发明人： Hiroshi Kubo , Hironobu Ito
IPC分类号： F16L3/12
CPC分类号： F16L3/1222
摘要： Intermediate coupler for hoses attachable to a vehicle body including a fitment body with hose joints at opposite ends and a mounting bracket caulkedly bound to an intermediate base portion of the fitment body. The fitment body has, at the intermediate base portion in a consecutively stepped manner, a bracket mounting portion and a flange provided on one side of the bracket mounting portion. The flange has a diameter larger than that of the bracket mounting portion. The mounting bracket has an insert hole provided with a tapered surface divergent toward its outer end face.
摘要翻译：用于可连接到车体的软管的中间联接器，其包括具有在相对端处的软管接头的配件主体和与该配件主体的中间基座部分嵌合的安装支架。配合体在中间基部处连续阶梯状地具有支架安装部和设置在支架安装部一侧的凸缘。凸缘的直径大于支架安装部分的直径。安装支架具有插入孔，该插入孔具有朝向其外端面发散的锥形表面。

5. 发明申请

US20120293960A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：US20120293960A1
公开(公告)日：2012-11-22
申请号：US13457920
申请日：2012-04-27
申请人： Hidetoshi Takashima , Hironobu Ito
发明人： Hidetoshi Takashima , Hironobu Ito
IPC分类号： H05K7/20 , H05K7/00
CPC分类号： G02F1/133308 , G02F1/133382 , G02F1/13452 , G02F2001/133314 , G02F2001/133317 , G02F2001/13332 , G02F2001/133322 , G02F2201/46 , G02F2201/503 , H05K5/02
摘要： A display device includes: a base plate being provided on a first side of a display panel; a front-face supporting member facing the base plate with the display panel therebetween, having a periphery on an external side with respect to the display panel, and being joined to the base plate at part or all of a peripheral portion of the front-face supporting member; and a back-face supporting member facing the front-face supporting member with the base plate therebetween, and being joined to both of the front-face supporting member and the base plate at a peripheral portion of the back-face supporting member.
摘要翻译：显示装置包括：底板，设置在显示面板的第一侧上; 面对所述基板的正面支撑构件，其间具有所述显示面板，在所述显示面板的外侧具有周边，并且在所述正面的周边部的一部分或全部与所述基板接合支持会员以及背面支撑构件，所述背面支撑构件面对所述前面支撑构件，所述基板在所述前面支撑构件之间，并且在所述背面支撑构件的周边部分处连接到所述正面支撑构件和所述基板的两者。

6. 发明授权

US06873209B2 Input buffer circuit having function of canceling offset voltage 失效
标题翻译：具有消除失调电压功能的输入缓冲电路
公开(公告)号：US06873209B2
公开(公告)日：2005-03-29
申请号：US10670217
申请日：2003-09-26
申请人： Kengo Takata , Tsutomu Yoshimura , Harufusa Kondo , Hironobu Ito
发明人： Kengo Takata , Tsutomu Yoshimura , Harufusa Kondo , Hironobu Ito
IPC分类号： H03K19/0175 , H03F3/45 , H04L25/02
CPC分类号： H03F3/45748 , H03F2203/45342 , H03F2203/45652
摘要： An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.
摘要翻译：获得了没有电路性能下降的输入缓冲器电路和与前一级电路的连接类型的限制。输出信号（OUTB）输入到第一低通滤波器电路，第一低通滤波器电路对输出信号（OUTB）进行积分。积分的结果作为电压值（V2a）存储在电容器（4s）中。以相同的方式，将输出信号（OUT）输入到第二低通滤波器电路，并且第二低通滤波器电路对输出信号（OUT）进行积分。积分的结果作为电压值（V2b）存储在电容器（4t）中。差分放大器电路（5）通过放大电压值（V2a和V2b），根据晶体管（1x和1y）的设计规格产生适当的电压（V3a和V3b）并将其输出。电压（V3a和V3b）分别施加在晶体管（1x和1y）的相应后栅上。

7. 发明授权

US06615339B1 VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively 失效
标题翻译：接受分支到连续执行的指令字中的指令的VLIW处理器
公开(公告)号：US06615339B1
公开(公告)日：2003-09-02
申请号：US09484413
申请日：2000-01-18
申请人： Hironobu Ito , Hisakazu Sato
发明人： Hironobu Ito , Hisakazu Sato
IPC分类号： G06F938
CPC分类号： G06F9/30167 , G06F9/30156 , G06F9/322 , G06F9/3822 , G06F9/3842
摘要： A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction word, and a program counter control unit controlling a value of a program counter for providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during a consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced. This renders it possible to branch to an operation instruction executed during a consecutive execution and thus provide an enhanced efficiency of instruction-code compression.
摘要翻译： VLIW处理器包括指令解码单元，其选择并行执行和连续执行中的一个并且解码包括在指令字中的多个操作指令，以及程序计数器控制单元，用于控制用于提供指令解码的指示的程序计数器的值单元提供在连续执行中提供的操作指令，并且在连续执行期间执行的操作指令之前执行的操作指令被分支到在连续执行期间执行的操作指令。这使得可以分支到在连续执行期间执行的操作指令，从而提供增强的指令代码压缩效率。

8. 发明授权

US06553474B2 Data processor changing an alignment of loaded data 失效
标题翻译：数据处理器更改加载数据的对齐
公开(公告)号：US06553474B2
公开(公告)日：2003-04-22
申请号：US09767901
申请日：2001-01-24
申请人： Hironobu Ito , Hisakazu Sato
发明人： Hironobu Ito , Hisakazu Sato
IPC分类号： G06F1500
CPC分类号： G06F9/30043 , G06F9/3816 , G06F12/04
摘要： A data processor in which a read operation, including misaligned data as operand data, can be performed in a single cycle. An alignment buffer having a register to hold data stored at one address in data memory is provided between the data memory and a data path unit. The alignment buffer outputs misaligned data by selecting misaligned data from data held in the register and data read from the data memory. The data held in the register is updated as word-aligned data is read out.
摘要翻译：其中可以在单个周期中执行包括不对准数据作为操作数数据的读取操作的数据处理器。具有存储在数据存储器中的一个地址处的数据的寄存器的对准缓冲器被提供在数据存储器和数据路径单元之间。对准缓冲器通过从保存在寄存器中的数据和从数据存储器读取的数据中选择未对齐的数据来输出未对准的数据。随着字对齐数据被读出，保存在寄存器中的数据被更新。

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