专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06414891B1 Semiconductor device including complementary data bus pair 有权
公开(公告)号：US06414891B1
公开(公告)日：2002-07-02
申请号：US09771889
申请日：2001-01-30
申请人： Shigehiro Kuge , Takeshi Hamamoto
发明人： Shigehiro Kuge , Takeshi Hamamoto
IPC分类号： G11C700
摘要： A semiconductor memory device includes a pair of complementary data buses, capacitive element corresponding to an even-numbered address, an equalize circuit and amplifier, capacitive element corresponding to an odd-numbered address, and an equalize circuit and amplifier. The pair of complementary data buses continuously transfer even-numbered address data and odd-numbered address data read out from the memory cell array in an alternating manner. The equalize circuit corresponding to the odd-numbered address is operated when the amplifier corresponding to the even-numbered address operates whereas the equalize circuit corresponding to the even-numbered address is operated when the amplifier corresponding to the odd-numbered address operates.

2. 发明授权

US06850454B2 Semiconductor memory device with reduced current consumption during standby state 失效
标题翻译：半导体存储器件在待机状态下具有降低的电流消耗
公开(公告)号：US06850454B2
公开(公告)日：2005-02-01
申请号：US10626643
申请日：2003-07-25
申请人： Shigehiro Kuge , Takeshi Hamamoto
发明人： Shigehiro Kuge , Takeshi Hamamoto
IPC分类号： G11C11/409 , G11C7/00 , G11C7/12 , G11C8/00 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4091 , G11C11/4094 , G11C29/00
CPC分类号： G11C29/832 , G11C7/12 , G11C11/4094 , G11C29/83 , G11C2207/2227
摘要： Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.
摘要翻译：指示存储器块中是否存在短路缺陷的数据被编程为熔丝编程电路。根据熔丝程序数据和模式指令信号，通过在特定模式中产生位线隔离指令信号的电路来切换块选择信号和对应的位线隔离指令信号之间的对应关系。在特定的操作模式中，可以将相应的读出放大器频带中存在泄漏电流路径的存储块隔开。至少在备用状态下的电流消耗降低。

3. 发明授权

US06438067B2 Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same 失效
标题翻译：时钟发生电路确保宽锁定频率范围并允许减少布局面积以及提供其的半导体器件
公开(公告)号：US06438067B2
公开(公告)日：2002-08-20
申请号：US09773637
申请日：2001-02-02
申请人： Shigehiro Kuge , Takeshi Hamamoto
发明人： Shigehiro Kuge , Takeshi Hamamoto
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/4076 , H03L7/0814 , H03L7/10
摘要： A DLL circuit includes a delay circuit for producing an output clock signal by delaying an input clock signal, and a phase comparator circuit for making a comparison between phases of the output and input clock signals. The delay circuit includes a plurality of delay units each having a unit delay amount changing in accordance with a drive potential level. The DLL circuit further includes a delay control circuit for controlling activation of the delay units in accordance with the result of phase comparison of the phase comparator circuit, and a drive potential control circuit for controlling the drive potential in accordance with the result of phase comparison of the phase comparator circuit.
摘要翻译： DLL电路包括用于通过延迟输入时钟信号来产生输出时钟信号的延迟电路，以及用于在输出和输入时钟信号的相位之间进行比较的相位比较器电路。延迟电路包括多个延迟单元，每个延迟单元具有根据驱动电位电平而改变的单位延迟量。 DLL电路还包括延迟控制电路，用于根据相位比较器电路的相位比较的结果控制延迟单元的激活，以及用于根据相位比较结果控制驱动电位的驱动电位控制电路相位比较电路。

4. 发明授权

US06781900B2 Semiconductor memory device with enhanced reliability 失效
标题翻译：具有增强可靠性的半导体存储器件
公开(公告)号：US06781900B2
公开(公告)日：2004-08-24
申请号：US10234256
申请日：2002-09-05
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
IPC分类号： G11C2900
CPC分类号： G11C29/027 , G11C29/02
摘要： The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.
摘要翻译：半导体存储器件具有作为工作模式的形式模式和测试模式。该程序电路包括熔丝元件，其中使用备用存储单元而不是有缺陷存储单元的地址被编程。程序电路确认在测试模式下比在正常模式下更严格的状态下的熔断器的断开状态。在测试模式和正常模式之间的结果不同的情况下，通过检测电路将异常通知给外部。在保险丝没有完全熔断的情况下，也可以在测试模式中检测这样的保险丝以排除有缺陷的芯片。

5. 发明申请

US20070285146A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070285146A1
公开(公告)日：2007-12-13
申请号：US11822184
申请日：2007-07-03
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： H03K3/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

6. 发明授权

US06809975B2 Semiconductor memory device having test mode and memory system using the same 失效
标题翻译：具有测试模式的半导体存储器件和使用其的存储器系统
公开(公告)号：US06809975B2
公开(公告)日：2004-10-26
申请号：US10274892
申请日：2002-10-22
申请人： Shigeru Yamaoka , Shigehiro Kuge
发明人： Shigeru Yamaoka , Shigehiro Kuge
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/1045 , G11C11/401 , G11C29/46
摘要： This DDR SDRAM includes a test mode entry signal generation circuit which sets a test mode entry signal at “H” level in accordance with a consecutive input of a first command, a second command, a test mode entry set command, a third command and a test mode register set command synchronously with a rising edge of a clock signal. This enables the DDR SDRAM to enter a test mode without using a high voltage. The DDR SDRAM can, therefore, enter the test mode even if it is incorporated into a registered DIMM.
摘要翻译：该DDR SDRAM包括测试模式输入信号产生电路，其根据第一命令，第二命令，测试模式输入设置命令，第三命令和第二命令的连续输入将测试模式输入信号设置为“H” 测试模式寄存器设置命令与时钟信号的上升沿同步。这使得DDR SDRAM能够进入测试模式而不使用高电压。因此，即使将DDR SDRAM合并到已注册的DIMM中，DDR SDRAM也可以进入测试模式。

7. 发明授权

US06731535B1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06731535B1
公开(公告)日：2004-05-04
申请号：US10455523
申请日：2003-06-06
申请人： Tsukasa Ooishi , Shuichi Ueno , Shigehiro Kuge
发明人： Tsukasa Ooishi , Shuichi Ueno , Shigehiro Kuge
IPC分类号： G11C1114
CPC分类号： H01L27/224 , G11C11/16 , H01L27/228
摘要： A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.
摘要翻译：非易失性半导体存储器件包括硅衬底，位线，字线和存储单元。位线位于硅衬底的主表面上方，并且字线被提供以与位线相交。存储单元位于位线和字线相交的区域，并且其一端电连接到位线，另一端电连接到字线。存储单元包括串联电连接的TMR元件和存取二极管。存取二极管包括n型硅层和通过熔融重结晶重结晶的p型硅层，并且在n型硅层和p型硅层之间的界面处具有pn结。结果，可以廉价地制造尺寸减小并且具有高性能的非易失性半导体存储器件。

8. 发明授权

US06388329B1 Semiconductor integrated circuit having three wiring layers 有权
标题翻译：具有三个布线层的半导体集成电路
公开(公告)号：US06388329B1
公开(公告)日：2002-05-14
申请号：US09705730
申请日：2000-11-06
申请人： Shigehiro Kuge , Kazutami Arimoto
发明人： Shigehiro Kuge , Kazutami Arimoto
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L27/10805 , H01L2924/0002 , H01L2924/3011 , Y10S257/903 , H01L2924/00
摘要： A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.
摘要翻译：分别形成分级供电结构的逆变器列的晶体管上层叠有高熔点金属布线层，第二铝布线层和第三铝布线层。采用高熔点金属布线层作为用于将晶体管彼此连接的局部线，第二铝布线层用作局部总线和分层电源线，第三铝布线层用作主母线和与各线相交的电源线。因此，布线层容易布局，而不需要与现有技术不同的主母线区域，并且可以减少布局面积。

9. 发明授权

US06715096B2 Interface circuit device for performing data sampling at optimum strobe timing by using stored data window information to determine the strobe timing 有权
标题翻译：接口电路装置，用于通过使用存储的数据窗口信息来确定选通定时，以最佳选通定时执行数据采样
公开(公告)号：US06715096B2
公开(公告)日：2004-03-30
申请号：US09749509
申请日：2000-12-28
申请人： Shigehiro Kuge
发明人： Shigehiro Kuge
IPC分类号： G06F104
CPC分类号： G06F13/4239 , G06F13/1689 , Y02D10/14 , Y02D10/151
摘要： An interface unit includes a timing control circuit for extracting an effective data window by detecting a point of change in a transferred data, and determining strobe timing for taking in the data in accordance with the extracted effective window; and a strobe clock generating circuit for generating a strobe clock signal for taking in the data under control of the timing control circuit. Regardless of the system structure, accurate data transfer is achieved between any semiconductor devices in the system.
摘要翻译：接口单元包括定时控制电路，用于通过检测传送数据的变化点来提取有效数据窗口，并根据所提取的有效窗口确定接收数据的选通定时; 以及选通时钟发生电路，用于在定时控制电路的控制下产生用于接收数据的选通时钟信号。无论系统结构如何，在系统中的任何半导体器件之间实现准确的数据传输。

10. 发明授权

US06424593B1 Semiconductor memory device capable of adjusting internal parameter 失效
标题翻译：半导体存储器能够调整内部参数
公开(公告)号：US06424593B1
公开(公告)日：2002-07-23
申请号：US09811580
申请日：2001-03-20
申请人： Shigehiro Kuge , Tetsuo Kato
发明人： Shigehiro Kuge , Tetsuo Kato
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1078 , G11C11/4093 , G11C2207/2254
摘要： Internal parameter control signal generating units generate internal parameter control signals for adjusting internal parameters of a semiconductor memory device. Each internal parameter control signal generating unit includes an anti-fuse element formed with a data holding capacitor of a memory cell. The anti-fuse element is blown with application of a high voltage according to a parameter adjustment signal to break down a dielectric film and then, act as a resistance element. The internal parameter control signal generating unit sets a signal level of a corresponding internal parameter control signal in a non-volatile manner according to the presence or absence of a blowing input to the anti-fuse element.
摘要翻译：内部参数控制信号发生单元产生用于调整半导体存储器件的内部参数的内部参数控制信号。每个内部参数控制信号产生单元包括由存储单元的数据保持电容器形成的反熔丝元件。根据参数调整信号，通过施加高电压来对抗熔丝元件进行熔断，分解电介质膜，然后作为电阻元件。内部参数控制信号生成部，根据是否存在向反熔丝元件的吹入输入，以非易失的方式设定相应的内部参数控制信号的信号电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式