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1. 发明授权

US07985998B2 Trench-type semiconductor device structure 有权
标题翻译：沟槽型半导体器件结构
公开(公告)号：US07985998B2
公开(公告)日：2011-07-26
申请号：US12177756
申请日：2008-07-22
申请人： Shian-Jyh Lin , Ming-Cheng Chang , Neng Tai Shih , Hung-Chang Liao
发明人： Shian-Jyh Lin , Ming-Cheng Chang , Neng Tai Shih , Hung-Chang Liao
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L28/55
摘要： A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.
摘要翻译：公开了一种沟槽型半导体器件结构。该结构包括半导体衬底，栅介质层和衬底沟道结构。半导体衬底包括具有上部和下部的沟槽。上部包括形成在其中的导电层。下部包括形成在其中的沟槽电容器。栅介质层位于半导体衬底和导电层之间。具有与沟槽相邻的开口的衬底沟道结构经由开口电连接到半导体衬底。

2. 发明申请

US20090166702A1 TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译： TRENCH型半导体器件结构
公开(公告)号：US20090166702A1
公开(公告)日：2009-07-02
申请号：US12177756
申请日：2008-07-22
申请人： Shian-Jyh LIN , Ming-Cheng Chang , Neng Tai Shih , Hung-Chang Liao
发明人： Shian-Jyh LIN , Ming-Cheng Chang , Neng Tai Shih , Hung-Chang Liao
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L28/55
摘要： A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.
摘要翻译：公开了一种沟槽型半导体器件结构。该结构包括半导体衬底，栅介质层和衬底沟道结构。半导体衬底包括具有上部和下部的沟槽。上部包括形成在其中的导电层。下部包括形成在其中的沟槽电容器。栅极电介质层位于半导体衬底和导电层之间。具有与沟槽相邻的开口的衬底沟道结构经由开口电连接到半导体衬底。

3. 发明授权

US08044449B2 Memory device with a length-controllable channel 有权
标题翻译：具有长度可控通道的存储器
公开(公告)号：US08044449B2
公开(公告)日：2011-10-25
申请号：US12183021
申请日：2008-07-30
申请人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
发明人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
摘要翻译：提供存储器件。存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离衬底的顶表面，形成在衬底中用作源极/漏极的沟槽的上部侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

4. 发明申请

US20110084325A1 DRAM STRUCTURE WITH A LOW PARASITIC CAPACITANCE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有低的PARASIIC电容的DRAM结构及其制造方法
公开(公告)号：US20110084325A1
公开(公告)日：2011-04-14
申请号：US12649361
申请日：2009-12-30
申请人： Hsiao-Lei Wang , Chung-Lin Huang , Hung-Chang Liao , Shih-Lung Chen
发明人： Hsiao-Lei Wang , Chung-Lin Huang , Hung-Chang Liao , Shih-Lung Chen
IPC分类号： H01L27/108 , H01L21/762
CPC分类号： H01L27/10894 , H01L21/76229 , H01L27/10897
摘要： An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.
摘要翻译：描述了一种用于堆叠DRAM栅极堆叠的氧化物间隔物，包括：具有存储器阵列区域和外围区域的半导体衬底，分别设置在存储器阵列区域和外围区域内的多个栅极，设置在栅极上的氧化硅间隔物其中多晶硅接触插塞通过多晶硅沉积和化学机械抛光形成。在形成多晶硅接触塞之后，沉积氧化硅层以隔离触点和栅极。通过化学机械抛光去除接触塞顶部的氧化硅层，实现平面化。

5. 发明授权

US06960530B2 Method of reducing the aspect ratio of a trench 有权
标题翻译：降低沟槽纵横比的方法
公开(公告)号：US06960530B2
公开(公告)日：2005-11-01
申请号：US10724435
申请日：2003-11-28
申请人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
发明人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
IPC分类号： H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/31116 , H01L21/31612
摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.
摘要翻译：减小沟槽纵横比的方法。在衬底中形成沟槽。通过HDPCVD在沟槽的表面上形成共形的富Si氧化物层。通过HDPCVD在富Si氧化物层上形成保形第一氧化物层。通过LPCVD在第一氧化物层上形成保形的第二氧化物层。通过各向异性蚀刻去除部分富Si氧化物层，第二氧化物层和第一氧化物层，以形成由剩余的富Si氧化物层，剩余的第二氧化物层和剩余的第一氧化物层组成的氧化物间隔物。剩余的第二氧化物层，剩余的第一氧化物层的一部分和富Si氧化物层的一部分被BOE除去。因此，剩余的第一和富Si氧化物层的一部分形成在沟槽的下表面上，从而减小沟槽纵横比。

6. 发明授权

US06153482A Method for fabricating LOCOS isolation having a planar surface which includes having the polish stop layer at a lower level than the LOCOS formation 有权
标题翻译：用于制造具有平坦表面的LOCOS隔离的方法，其包括使抛光停止层处于比LOCOS形成更低的水平
公开(公告)号：US06153482A
公开(公告)日：2000-11-28
申请号：US174091
申请日：1998-10-16
申请人： Lin-Chin Su , Tzu-Ching Tsai , Miin-Jiunn Jiang , Hung-Chang Liao , Jim Wang , Chung Min Lin
发明人： Lin-Chin Su , Tzu-Ching Tsai , Miin-Jiunn Jiang , Hung-Chang Liao , Jim Wang , Chung Min Lin
IPC分类号： H01L21/762 , H01L21/331 , H01L21/302 , H01L21/76
CPC分类号： H01L21/76205
摘要： A method for fabricating LOCOS isolation having a planar surface. The method utilizes a polysilicon spacer to prevent bird beak. The method adds the steps of forming a polishing stop layer and removing said edge-protrusion portion of the local oxide by chemical mechanical polishing.
摘要翻译：一种用于制造具有平坦表面的LOCOS隔离的方法。该方法利用多晶硅间隔物来防止鸟嘴。该方法通过化学机械抛光添加形成抛光停止层并去除局部氧化物的边缘突出部分的步骤。

7. 发明申请

US20080142862A1 METHOD OF FABRICATING A TRENCH CAPACITOR HAVING INCREASED CAPACITANCE 审中-公开
标题翻译：制造具有增加电容的TRENCH电容器的方法
公开(公告)号：US20080142862A1
公开(公告)日：2008-06-19
申请号：US12037090
申请日：2008-02-26
申请人： Sam Liao , Meng-Hung Chen , Hung-Chang Liao
发明人： Sam Liao , Meng-Hung Chen , Hung-Chang Liao
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/1087
摘要： The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-generation trench DRAM devices. A large-capacitance trench capacitor is first fabricated in the silicon substrate. An epitaxial silicon layer is then grown on the silicon substrate. Active areas, shallow trench isolation regions, and gate conductors are formed on/in the epitaxial silicon layer.
摘要翻译：本发明涉及制造具有增加的电容的沟槽电容器的方法。为了解决蚀刻具有非常高的纵横比的深沟槽的难题，在下一代沟槽DRAM器件的制造中采用外延硅生长工艺。首先在硅衬底中制造大电容沟槽电容器。然后在硅衬底上生长外延硅层。活性区域，浅沟槽隔离区域和栅极导体形成在外延硅层中/之上。

8. 发明申请

US20070045699A1 METHOD OF FABRICATING A TRENCH CAPACITOR HAVING INCREASED CAPACITANCE 审中-公开
标题翻译：制造具有增加电容的TRENCH电容器的方法
公开(公告)号：US20070045699A1
公开(公告)日：2007-03-01
申请号：US11466105
申请日：2006-08-22
申请人： Sam Liao , Meng-Hung Chen , Hung-Chang Liao
发明人： Sam Liao , Meng-Hung Chen , Hung-Chang Liao
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/1087
摘要： The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-generation trench DRAM devices. A large-capacitance trench capacitor is first fabricated in the silicon substrate. An epitaxial silicon layer is then grown on the silicon substrate. Active areas, shallow trench isolation regions, and gate conductors are formed on/in the epitaxial silicon layer.
摘要翻译：本发明涉及制造具有增加的电容的沟槽电容器的方法。为了解决蚀刻具有非常高的纵横比的深沟槽的难题，在下一代沟槽DRAM器件的制造中采用外延硅生长工艺。首先在硅衬底中制造大电容沟槽电容器。然后在硅衬底上生长外延硅层。活性区域，浅沟槽隔离区域和栅极导体形成在外延硅层中/之上。

9. 发明授权

US08466504B2 DRAM with dopant stop layer and method of fabricating the same 有权
标题翻译：具有掺杂剂停止层的DRAM及其制造方法
公开(公告)号：US08466504B2
公开(公告)日：2013-06-18
申请号：US13231968
申请日：2011-09-14
申请人： Chia-Ming Yang , Yao-Hsien Wang , Chen-Kang Wei , Chien-Chi Lee , Ming Yean , Yi-Wei Chuang , Hsiao-Lung Chiang , Hung-Chang Liao , Chung-Yuan Lee , Ming-Chi Chao
发明人： Chia-Ming Yang , Yao-Hsien Wang , Chen-Kang Wei , Chien-Chi Lee , Ming Yean , Yi-Wei Chuang , Hsiao-Lung Chiang , Hung-Chang Liao , Chung-Yuan Lee , Ming-Chi Chao
IPC分类号： H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L21/26506 , H01L21/26586 , H01L29/1083
摘要： A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.
摘要翻译：具有掺杂剂停止层的DRAM包括衬底，沟槽型晶体管和电连接到沟槽型晶体管的电容器。沟槽型晶体管包括嵌入在衬底中的栅极结构。源极掺杂区域和漏极掺杂区域设置在栅极结构的两侧的衬底中。硼掺杂区域设置在源极掺杂区域下方。掺杂剂停止层设置在硼掺杂区域内或硼掺杂区域的下方。掺杂剂停止层包括选自C，Si，Ge，Sn，Cl，F和Br的掺杂剂。

10. 发明申请

US20120280297A1 DRAM WITH DOPANT STOP LAYER AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有停留层的DRAM及其制造方法
公开(公告)号：US20120280297A1
公开(公告)日：2012-11-08
申请号：US13231968
申请日：2011-09-14
申请人： Chia-Ming Yang , Yao-Hsien Wang , Chen-Kang Wei , Chien-Chi Lee , Ming Yean , Yi-Wei Chuang , Hsiao-Lung Chiang , Hung-Chang Liao , Chung-Yuan Lee , Ming-Chi Chao
发明人： Chia-Ming Yang , Yao-Hsien Wang , Chen-Kang Wei , Chien-Chi Lee , Ming Yean , Yi-Wei Chuang , Hsiao-Lung Chiang , Hung-Chang Liao , Chung-Yuan Lee , Ming-Chi Chao
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L21/26506 , H01L21/26586 , H01L29/1083
摘要： A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.
摘要翻译：具有掺杂剂停止层的DRAM包括衬底，沟槽型晶体管和电连接到沟槽型晶体管的电容器。沟槽型晶体管包括嵌入在衬底中的栅极结构。源极掺杂区域和漏极掺杂区域设置在栅极结构的两侧的衬底中。硼掺杂区域设置在源极掺杂区域下方。掺杂剂停止层设置在硼掺杂区域内或硼掺杂区域的下方。掺杂剂停止层包括选自C，Si，Ge，Sn，Cl，F和Br的掺杂剂。

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