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1. 发明授权

US06960530B2 Method of reducing the aspect ratio of a trench 有权
标题翻译：降低沟槽纵横比的方法
公开(公告)号：US06960530B2
公开(公告)日：2005-11-01
申请号：US10724435
申请日：2003-11-28
申请人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
发明人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
IPC分类号： H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/31116 , H01L21/31612
摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.
摘要翻译：减小沟槽纵横比的方法。在衬底中形成沟槽。通过HDPCVD在沟槽的表面上形成共形的富Si氧化物层。通过HDPCVD在富Si氧化物层上形成保形第一氧化物层。通过LPCVD在第一氧化物层上形成保形的第二氧化物层。通过各向异性蚀刻去除部分富Si氧化物层，第二氧化物层和第一氧化物层，以形成由剩余的富Si氧化物层，剩余的第二氧化物层和剩余的第一氧化物层组成的氧化物间隔物。剩余的第二氧化物层，剩余的第一氧化物层的一部分和富Si氧化物层的一部分被BOE除去。因此，剩余的第一和富Si氧化物层的一部分形成在沟槽的下表面上，从而减小沟槽纵横比。

2. 发明申请

US20050124127A1 Method for manufacturing gate structure for use in semiconductor device 审中-公开
标题翻译：制造用于半导体器件的栅极结构的方法
公开(公告)号：US20050124127A1
公开(公告)日：2005-06-09
申请号：US10726500
申请日：2003-12-04
申请人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
发明人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L29/49 , H01L29/51
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/51 , H01L29/517 , H01L29/518
摘要： The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上依次形成栅极电介质层，多晶硅层，金属层，势垒层和钨层，在氮气环境中进行快速热退火（RTA）在所述钨层上形成氮化硅层，并将所述多层薄膜结构图案化为规定的形态。

3. 发明申请

US20050020059A1 Method for forming aluminum-containing interconnect 审中-公开
标题翻译：含铝互连的形成方法
公开(公告)号：US20050020059A1
公开(公告)日：2005-01-27
申请号：US10800695
申请日：2004-03-16
申请人： Yi-Nan Chen , Kuo-Chien Wu
发明人： Yi-Nan Chen , Kuo-Chien Wu
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76852
摘要： A method for forming an aluminum-containing interconnect is provided. The method includes providing a substrate with a contact region. A first barrier layer, an aluminum-containing conductive layer, and a second barrier layer are sequentially formed over the substrate, and then patterned to form an aluminum-containing interconnect. The aluminum-containing interconnect is electrically coupled to the contact region and has a sidewall exposed. A barrier spacer is formed on the sidewall of the aluminum-containing interconnect by using a material selected from a group consisting of titanium, titanium nitride, and the combination thereof.
摘要翻译：提供一种形成含铝互连的方法。该方法包括向基板提供接触区域。依次在基板上形成第一阻挡层，含铝导电层和第二阻挡层，然后将其图案化以形成含铝互连。含铝互连件电耦合到接触区域并具有暴露的侧壁。通过使用选自钛，氮化钛及其组合的材料，在含铝互连件的侧壁上形成阻挡隔离物。

4. 发明授权

US07052949B2 Method for forming bit line 有权
标题翻译：位线形成方法
公开(公告)号：US07052949B2
公开(公告)日：2006-05-30
申请号：US10459327
申请日：2003-06-11
申请人： Kuo-Chien Wu , Tse-Yao Huang , Yi-Nan Chen
发明人： Kuo-Chien Wu , Tse-Yao Huang , Yi-Nan Chen
IPC分类号： H01L21/4763 , H01L21/8238
CPC分类号： H01L21/76802 , H01L27/10888 , H01L27/10894
摘要： A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.
摘要翻译：一种形成位线的方法。提供半导体衬底。在半导体衬底上形成具有栅极和S / D区域的MOS。在半导体衬底上形成具有第一开口的第一电介质层，以暴露S / D区域。在第一开口中形成导电层。在第一电介质层和导电层的表面上形成阻挡层。具有第二开口和第三开口的第二电介质层形成在阻挡层上，第二开口的位置对应于第一开口。分别在第二开口和第三开口中形成金属层作为位线。

5. 发明申请

US20050277258A1 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US20050277258A1
公开(公告)日：2005-12-15
申请号：US10940707
申请日：2004-09-15
申请人： Tse-Yao Huang , Kuo-Chien Wu , Yi-Nan Chen
发明人： Tse-Yao Huang , Kuo-Chien Wu , Yi-Nan Chen
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L27/10 , H01L27/105
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L27/105 , H01L27/1052
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：在晶体管的栅极结构和扩散区上形成薄的氮化物绝缘层; 形成第一绝缘层，然后将其平坦化以暴露栅极结构上的氮化物绝缘层; 蚀刻穿过第一绝缘层以形成接触孔的第一部分; 在所述接触孔的所述第一部分中形成接触的第一部分; 形成第二绝缘层; 蚀刻穿过第二绝缘层以形成接触孔的第二部分; 以及在接触孔的第二部分中形成接触的第二部分。用于形成导电接触的两级蚀刻工艺有效地防止了字线和位线之间的过蚀刻和短路。

6. 发明授权

US06797564B1 Method of forming bit lines and bit line contacts in a memory device 有权
标题翻译：在存储器件中形成位线和位线接触的方法
公开(公告)号：US06797564B1
公开(公告)日：2004-09-28
申请号：US10605401
申请日：2003-09-29
申请人： Kuo-Chien Wu , Yi-Nan Chen
发明人： Kuo-Chien Wu , Yi-Nan Chen
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L27/10885 , H01L27/10888
摘要： A method for forming bit lines and bit line contacts in a memory device is provided. A conductive layer is formed over a substrate to cover a plurality of gate structures thereon. A chemical-mechanical polishing operation is performed to polish the conductive layer so that a cap layer of the gate structures is exposed. A portion of the conductive layer is removed so that only the conductive layer between two neighboring gate structures is retained to serve as a bit line contact. A bit line is formed over the substrate such that the bit line and the bit line contact are electrically connected. Because the bit line contact has a smaller dimension compared with a bit line contact formed using the conventional method, the possibility of having a short circuit between a bit line contact and an adjacent bit line is reduced.
摘要翻译：提供了一种在存储器件中形成位线和位线接触的方法。导电层形成在衬底上以覆盖其上的多个栅极结构。进行化学机械抛光操作以抛光导电层，使得栅极结构的盖层暴露。导电层的一部分被去除，使得仅保持两个相邻栅极结构之间的导电层以用作位线接触。在衬底上形成位线，使得位线和位线接触电连接。由于与使用常规方法形成的位线接触相比，位线接触具有较小的尺寸，因此减少了位线接触和相邻位线之间短路的可能性。

7. 发明授权

US07115491B2 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US07115491B2
公开(公告)日：2006-10-03
申请号：US10940707
申请日：2004-09-15
申请人： Tse-Yao Huang , Kuo-Chien Wu , Yi-Nan Chen
发明人： Tse-Yao Huang , Kuo-Chien Wu , Yi-Nan Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L27/105 , H01L27/1052
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：在晶体管的栅极结构和扩散区上形成薄的氮化物绝缘层; 形成第一绝缘层，然后将其平坦化以暴露栅极结构上的氮化物绝缘层; 蚀刻穿过第一绝缘层以形成接触孔的第一部分; 在所述接触孔的所述第一部分中形成接触的第一部分; 形成第二绝缘层; 蚀刻穿过第二绝缘层以形成接触孔的第二部分; 以及在接触孔的第二部分中形成接触的第二部分。用于形成导电触点的两级蚀刻工艺有效地防止了字线和位线之间的过蚀刻和短路。

8. 发明授权

US06991978B2 World line structure with single-sided partially recessed gate structure 有权
标题翻译：世界线结构采用单面部分凹陷门结构
公开(公告)号：US06991978B2
公开(公告)日：2006-01-31
申请号：US10858032
申请日：2004-06-01
申请人： Shih-Fan Kuan , Kuo-Chien Wu
发明人： Shih-Fan Kuan , Kuo-Chien Wu
IPC分类号： H01L29/72
CPC分类号： H01L27/10891 , H01L21/28114 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L29/42376 , H01L29/6653 , H01L29/6656
摘要： A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.
摘要翻译：具有单面部分凹陷栅结构的字线结构。字线结构包括栅极结构，第一栅极隔离物和第二栅极间隔物。栅极结构包括栅极介电层，第一栅极层，第二栅极层和栅极覆盖层，并且具有与第二栅极层的相对侧壁之一相邻的凹陷区域。第一栅极间隔物设置在栅极介电层和第一栅极层的相对侧壁上。第二栅极间隔物设置在栅极结构的相对侧壁上并且覆盖第一栅极间隔物。还公开了一种用于形成具有单面部分凹陷栅极结构的字线结构的方法。

9. 发明申请

US20050202666A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050202666A1
公开(公告)日：2005-09-15
申请号：US10709591
申请日：2004-05-17
申请人： Sweehan J.H. Yang , Kuo-Chien Wu , Shih-Fan Kuan
发明人： Sweehan J.H. Yang , Kuo-Chien Wu , Shih-Fan Kuan
IPC分类号： H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/76
CPC分类号： H01L21/76816 , H01L21/76897 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.
摘要翻译：一种制造半导体器件的方法。在基板上形成具有盖层的堆叠栅极结构和具有暴露盖层的顶表面的第一介电层。形成缓冲层以覆盖基板的第一区域中的电介质层和盖层。去除衬底的第二区域中的一部分盖层，使得盖层具有小于或等于缓冲层的厚度。第二介质层形成在衬底上。第二介电层的一部分和缓冲层下面的第一介电层被蚀刻以形成位线接触开口。同时，第二电介质层的一部分和下面的盖层被蚀刻以形成栅极接触开口。

10. 发明申请

US20050032389A1 Method for avoiding erosion of DRAM fuse sidewall 审中-公开
标题翻译：避免DRAM保险丝侧壁侵蚀的方法
公开(公告)号：US20050032389A1
公开(公告)日：2005-02-10
申请号：US10633525
申请日：2003-08-05
申请人： Kuo-Chien Wu
发明人： Kuo-Chien Wu
IPC分类号： H01L21/302 , H01L21/461 , H01L23/525 , H01L27/108
CPC分类号： H01L23/5258 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for avoiding the erosion of DRAM fuse sidewall. The method comprises the steps of forming a fuse on a substrate, depositing a dielectric layer on the substrate and the fuse, depositing operation layers on the dielectric layer to construct an intermediate structure, applying photoresist to the intermediate structure and etching the same to form a fuse opening so that the fuse is exposed, removing the photoresist, depositing a separate layer to cover at least the exposed portion of the fuse, and etching the separate layer so that the left separate layer covers at least the sidewall of the fuse. Disclosed also is a fuse structure of a DRAM. The fuse structure is characterized in that the sidewall of the fuse is covered with a separate layer having protecting function. Therefore, it is avoided that water left at the lower portion of the fuse in cleaning step reacts with the sidewall of the fuse to cause the damage of the structure.
摘要翻译：公开了一种避免DRAM熔丝侧壁侵蚀的方法。该方法包括以下步骤：在衬底上形成保险丝，在衬底和熔丝上沉积电介质层，在介电层上沉积操作层以构造中间结构，将光致抗蚀剂施加到中间结构上并蚀刻其形成保险丝开口，使得保险丝暴露，去除光致抗蚀剂，沉积单独的层以至少覆盖保险丝的暴露部分，并蚀刻分开的层，使得左分离层至少覆盖保险丝的侧壁。还公开了一种DRAM的熔丝结构。熔丝结构的特征在于，保险丝的侧壁被具有保护功能的单独的层覆盖。因此，避免了在保险丝的下部保留的水与保险丝的侧壁反应而导致结构的损坏。

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