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1. 发明申请

US20080037330A1 RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY 有权
标题翻译：用于双位闪存存储器的RAMP GATE擦除
公开(公告)号：US20080037330A1
公开(公告)日：2008-02-14
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

2. 发明申请

US20080151644A1 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US20080151644A1
公开(公告)日：2008-06-26
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

3. 发明授权

US07561471B2 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US07561471B2
公开(公告)日：2009-07-14
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

4. 发明授权

US07319615B1 Ramp gate erase for dual bit flash memory 有权
标题翻译：用于双位闪存的斜坡栅极擦除
公开(公告)号：US07319615B1
公开(公告)日：2008-01-15
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

5. 发明申请

US20080153274A1 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US20080153274A1
公开(公告)日：2008-06-26
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L21/425 , G11C11/34
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

6. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

7. 发明授权

US07671405B2 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US07671405B2
公开(公告)日：2010-03-02
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L27/112 , H01L21/336
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

8. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

9. 发明授权

US07944742B2 Diode assisted switching spin-transfer torque memory unit 有权
标题翻译：二极管辅助开关自旋转移转矩存储单元
公开(公告)号：US07944742B2
公开(公告)日：2011-05-17
申请号：US12861932
申请日：2010-08-24
申请人： Xuguang Wang , Yiran Chen , Dimitar V. Dimitrov , Hongyue Liu , Xiaobin Wang
发明人： Xuguang Wang , Yiran Chen , Dimitar V. Dimitrov , Hongyue Liu , Xiaobin Wang
IPC分类号： G11C11/14
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1659
摘要： A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
摘要翻译：存储器阵列包括位线和源极线的交叉点阵列。存储器设置在交叉点阵列的交叉点处。存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。晶体管电连接在磁性隧道结数据单元与位线或源极线之间，二极管与磁性隧道结数据单元处于热或电接触以辅助电阻状态切换。

10. 发明授权

US07786463B2 Non-volatile multi-bit memory with programmable capacitance 有权
标题翻译：带可编程电容的非易失性多位存储器
公开(公告)号：US07786463B2
公开(公告)日：2010-08-31
申请号：US12123685
申请日：2008-05-20
申请人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
发明人： Xuguang Wang , Shuiyuan Huang , Dimitar V. Dimitrov , Michael Xuefei Tang , Song S. Xue
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , G11C16/0475 , H01L45/1206 , H01L45/1266 , H01L45/143 , H01L45/1658
摘要： Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source.
摘要翻译：公开了具有可编程电容的非易失性多位存储器。说明性数据存储单元包括包括源极区和漏极区的衬底。第一绝缘层在衬底上。第一固体电解质电池在绝缘层之上并且具有在至少两个状态之间可控并且在源极区附近的电容。第二固体电解质电池在绝缘层之上，并且具有在至少两个状态之间可控的并且在漏极区附近的电容或电阻。绝缘元件将第一固体电解质电池与第二固体电解质电池隔离。第一阳极电耦合到第一固体电解质电池。第一固体电解质电池在阳极和绝缘层之间。第二阳极电耦合到第二固体电解质电池。第二固体电解质电池在阳极和绝缘层之间。栅极接触层在衬底上并且在源极区域和漏极区域之间并且与第一阳极和第二阳极电连接。栅极接触层电耦合到电压源。

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