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1. 发明申请

US20080037330A1 RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY 有权
标题翻译：用于双位闪存存储器的RAMP GATE擦除
公开(公告)号：US20080037330A1
公开(公告)日：2008-02-14
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

2. 发明授权

US07319615B1 Ramp gate erase for dual bit flash memory 有权
标题翻译：用于双位闪存的斜坡栅极擦除
公开(公告)号：US07319615B1
公开(公告)日：2008-01-15
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

3. 发明申请

US20080151644A1 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US20080151644A1
公开(公告)日：2008-06-26
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

4. 发明授权

US07561471B2 Cycling improvement using higher erase bias 有权
标题翻译：使用更高的擦除偏置循环改进
公开(公告)号：US07561471B2
公开(公告)日：2009-07-14
申请号：US11724711
申请日：2007-03-16
申请人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
发明人： Sheung-Hee Park , Xuguang Wang , Wing Leung , Ming-Sang Kwan , Yi He , Edward Franklin Runnion
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/14
摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
摘要翻译：提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

5. 发明申请

US20080151636A1 REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES 有权
标题翻译：用于闪存存储器件的重复擦除验证技术
公开(公告)号：US20080151636A1
公开(公告)日：2008-06-26
申请号：US11615710
申请日：2006-12-22
申请人： Sheung-Hee Park , Ming Kwan , Wing Leung
发明人： Sheung-Hee Park , Ming Kwan , Wing Leung
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/345
摘要： Erase verify operations as described herein can be utilized for a flash memory device having an array of memory cells. The erase verify operations employ repetitive erase verify testing to double-check previously verified bits that might otherwise relax or settle into an under-erased state. Following an initial erase verify procedure, an erase verify operation may perform a secondary erase verify procedure and apply additional erase pulses to bits that have become under-erased.
摘要翻译：如本文所述的擦除验证操作可以用于具有存储器单元阵列的闪存器件。擦除验证操作使用重复的擦除验证测试来对先前验证的位进行双重检查，否则这些位可能会松弛或置于欠擦除状态。在初始擦除验证过程之后，擦除验证操作可以执行次擦除验证过程，并且对已经被擦除的位施加附加的擦除脉冲。

6. 发明授权

US07385851B1 Repetitive erase verify technique for flash memory devices 有权
标题翻译：闪存设备的重复擦除验证技术
公开(公告)号：US07385851B1
公开(公告)日：2008-06-10
申请号：US11615710
申请日：2006-12-22
申请人： Sheung-Hee Park , Ming Kwan , Wing Leung
发明人： Sheung-Hee Park , Ming Kwan , Wing Leung
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/345
摘要： Erase verify operations as described herein can be utilized for a flash memory device having an array of memory cells. The erase verify operations employ repetitive erase verify testing to double-check previously verified bits that might otherwise relax or settle into an under-erased state. Following an initial erase verify procedure, an erase verify operation may perform a secondary erase verify procedure and apply additional erase pulses to bits that have become under-erased.
摘要翻译：如本文所述的擦除验证操作可以用于具有存储器单元阵列的闪存器件。擦除验证操作使用重复的擦除验证测试来对先前验证的位进行双重检查，否则这些位可能会松弛或置于欠擦除状态。在初始擦除验证过程之后，擦除验证操作可以执行次擦除验证过程，并且对已经被擦除的位施加附加的擦除脉冲。

7. 发明授权

US07283398B1 Method for minimizing false detection of states in flash memory devices 有权
标题翻译：用于最小化闪速存储器件中的状态的错误检测的方法
公开(公告)号：US07283398B1
公开(公告)日：2007-10-16
申请号：US10838962
申请日：2004-05-04
申请人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
发明人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
摘要翻译：本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。多个字线被布置成多行。多个位线被布置在多个列中。该方法通过确定与一列存储器单元相关联的所选位线开始。然后，该方法通过在一个负电压下偏置一组字线来继续。字线组电耦合到相关联的存储器单元。当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

8. 发明申请

US20050006606A1 Missing die detection 有权
标题翻译：缺失检测
公开(公告)号：US20050006606A1
公开(公告)日：2005-01-13
申请号：US10618297
申请日：2003-07-11
申请人： Fan Wang , Wing Leung
发明人： Fan Wang , Wing Leung
IPC分类号： H01L21/66 , H01L21/00 , G01V8/00
CPC分类号： H01L21/67259
摘要： An indication of whether or not a target object is present at a site of a collet assembly is derived by monitoring light reflected from the site. The use of reflected light enables the presence of objects to be detected, especially transparent objects. In a preferred arrangement for determining if a sapphire die is present in a die-handling collet assembly, light from a source is collimated or focused into a narrow beam and directed through a beam splitter at the target site of the collet assembly. Light reflected from the surface of the die is further reflected by the beam splitter toward a photo-sensor. The reflected light is measured when the collet passes over a dark background while on the way to deliver a die at a bonding position and again while returning after attempting to place the die at the bonding position. A determination of a die present in the former and absent in the latter is indicative of a well-placed die at the bonding position.
摘要翻译：通过监视从站点反射的光来导出目标对象是否存在于夹头组件的位置的指示。反射光的使用使得能够检测物体的存在，特别是透明物体。在用于确定裸片处理夹头组件中是否存在蓝宝石模具的优选布置中，来自源的光被准直或聚焦成窄梁并且被引导通过在夹头组件的目标位置处的分束器。从模具表面反射的光被分束器进一步反射成光传感器。当夹头在暗背景上通过时，测量反射光，同时在尝试将模具置于结合位置时在退出时再次在接合位置传送模具。存在于前者中并且在后者中不存在的模具的确定指示在结合位置处的良好的模具。

9. 发明申请

US20130267613A1 MOLECULAR-DETERMINANT BASED TYPING OF KIR ALLELES AND KIR-LIGANDS 审中-公开
标题翻译：基于分子决定子的基因型和基尔配偶
公开(公告)号：US20130267613A1
公开(公告)日：2013-10-10
申请号：US13877006
申请日：2011-10-05
申请人： Wing Leung , Rafijul Bari
发明人： Wing Leung , Rafijul Bari
IPC分类号： C12Q1/68
CPC分类号： C12Q1/6883 , C12Q2600/156 , C12Q2600/16 , G01N33/5047 , G01N33/566 , G01N33/56972 , G01N2333/705
摘要： The present invention relates to an assay to perform a molecular determinant-based functional killer immunoglobulin-like receptors (KIR) allele typing and ligand typing. In particular the present invention provides methods, compositions, and kits for a single nucleotide polymorphism (SNP) assay to type various allele groups of KIR2DL1 and KIR ligand with distinct functional properties based on polymorphism at position 245 in KIR2DL1, position 77 in HLA-C, and position 83 in HLA-B and HLA-A. The assays are suitable for use in predicting NK cell activity in health, disease, and transplantation.
摘要翻译：本发明涉及进行基于分子决定簇的功能性杀伤免疫球蛋白样受体（KIR）等位基因分型和配体分型的测定。特别地，本发明提供用于单核苷酸多态性（SNP）测定的方法，组合物和试剂盒，其基于KIR2DL1中的位置245，HLA-C中77位的多态性，键入具有不同功能特性的KIR2DL1和KIR配体的各种等位基因组，HLA-B和HLA-A位置83。该测定适用于预测健康，疾病和移植中的NK细胞活性。

10. 发明申请

US20080004753A1 Systems for and methods of characterizing reactions 审中-公开
标题翻译：表征反应的系统和方法
公开(公告)号：US20080004753A1
公开(公告)日：2008-01-03
申请号：US11801217
申请日：2007-05-08
申请人： Jong Hong , Douglas Goodwin , Eduardus Duin , Sachin Jambovane , Robert Moore , Taek-Jeong Nam , Se-Kown Kim , Wing Leung , Po Cheng
发明人： Jong Hong , Douglas Goodwin , Eduardus Duin , Sachin Jambovane , Robert Moore , Taek-Jeong Nam , Se-Kown Kim , Wing Leung , Po Cheng
IPC分类号： G01N33/53 , G01N33/50 , G05B21/00
CPC分类号： B01L3/502715 , B01L3/5025 , B01L2300/0816 , B01L2300/0861 , B01L2300/0864 , B01L2300/0867 , B01L2300/0874 , B01L2300/1827 , B01L2400/0487
摘要： An automated and computerized system for characterizing kinetic activities is disclosed. The system includes an optical unit with a controller chip. The controller chip has multiple reaction cells for simultaneously reacting samples of the catalyst under a range of reaction conditions and for optically monitoring the kinetic activity within each of the reaction cells; The system also preferably includes a temperature controller in thermal contact with the controller chip and an actuation device coupled to the controller chip for injecting and mixing samples of the catalyst with reagents into each of the reaction cells to form a product.
摘要翻译：公开了用于表征动力学活动的自动化和计算机化系统。该系统包括具有控制器芯片的光学单元。控制器芯片具有多个反应池，用于在一定范围的反应条件下同时反应催化剂样品，并用于光学监测每个反应池内的动力学活性; 该系统还优选地包括与控制器芯片热接触的温度控制器和耦合到控制器芯片的致动装置，用于将催化剂样品注入并混合到每个反应池中以形成产物。

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