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1. 发明授权

US5046046A Redundancy CAM using word line from memory 失效
标题翻译：冗余CAM使用内存中的字线
公开(公告)号：US5046046A
公开(公告)日：1991-09-03
申请号：US321904
申请日：1978-03-10
申请人： Sherif Sweha , Mark Bauer , Phil Kliza
发明人： Sherif Sweha , Mark Bauer , Phil Kliza
IPC分类号： G11C29/00
CPC分类号： G11C29/785
摘要： A redundancy programming circuit employing a two EPROM cell CAM for storing programmed states of redundant elements. The CAMs are disposed aside a memory array and word lines of the array are extended to the CAMs for programming the CAMs. Two word lines are coupled to each EPROM cell so that programming can still be achieved in the event one of the lines is defective.
摘要翻译：一种冗余编程电路，采用两个EPROM单元CAM来存储冗余元件的编程状态。将CAM放置在存储器阵列的旁边，阵列的字线被扩展到CAM用于对CAM进行编程。两个字线耦合到每个EPROM单元，使得在一条线路有缺陷的情况下，仍然可以实现编程。

2. 发明授权

US5781472A Bit map addressing schemes for flash/memory 失效
公开(公告)号：US5781472A
公开(公告)日：1998-07-14
申请号：US851104
申请日：1997-05-02
申请人： Sherif Sweha , Mark E. Bauer
发明人： Sherif Sweha , Mark E. Bauer
IPC分类号： G11C16/06 , G11C8/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C2211/5631 , G11C2211/5632 , G11C2211/5642 , G11C8/00
摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

3. 发明授权

US5822256A Method and circuitry for usage of partially functional nonvolatile memory 失效
标题翻译：用于部分功能非易失性存储器的方法和电路
公开(公告)号：US5822256A
公开(公告)日：1998-10-13
申请号：US811194
申请日：1997-03-05
申请人： Mark E. Bauer , Steven Wells , David M. Brown , Johnny Javanifard , Sherif Sweha , Robert N. Hasbun , Gary J. Gallagher , Mamun Rashid , Rodney R. Rozman , Glen Hawk , George Blanchard , Mark Winston , Richard D. Pashley
发明人： Mark E. Bauer , Steven Wells , David M. Brown , Johnny Javanifard , Sherif Sweha , Robert N. Hasbun , Gary J. Gallagher , Mamun Rashid , Rodney R. Rozman , Glen Hawk , George Blanchard , Mark Winston , Richard D. Pashley
IPC分类号： G11C11/56 , G11C29/00 , G11C29/44 , G11C7/00
CPC分类号： G11C29/88 , G11C11/5621 , G11C11/5628 , G11C29/44 , G11C2211/5641
摘要： A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.
摘要翻译：描述了允许使用部分功能的集成电路存储器的方法和电路。存储器阵列被分离成单独的块，每个块可以被隔离以最小化由缺陷使得不可用的存储器阵列的量。还提供电路以将阵列内的存储器单元编程为至少三个电荷量之一，从而增加剩余功能块提供的存储量。

4. 发明授权

US5815443A Bit map addressing schemes for flash memory 失效
公开(公告)号：US5815443A
公开(公告)日：1998-09-29
申请号：US634953
申请日：1996-04-19
申请人： Sherif Sweha , Mark E. Bauer
发明人： Sherif Sweha , Mark E. Bauer
IPC分类号： G11C16/06 , G11C8/00 , G11C11/56 , G11C16/02 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C2211/5631 , G11C2211/5632 , G11C2211/5642 , G11C8/00
摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

5. 发明授权

US06483742B1 Bit map addressing schemes for flash memory 失效
标题翻译：闪存的位图寻址方案
公开(公告)号：US06483742B1
公开(公告)日：2002-11-19
申请号：US08641046
申请日：1996-04-19
申请人： Sherif Sweha , Mark E. Bauer
发明人： Sherif Sweha , Mark E. Bauer
IPC分类号： G11C1604
CPC分类号： G11C11/5621 , G11C8/00 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C2211/5631 , G11C2211/5632 , G11C2211/5642
摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. “By-output” architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. “By-address” architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.
摘要翻译：公开了用于具有存储n个二进制位的存储器单元的存储器件的读和写访问的读取路径和写入路径体系结构。 “副输出”架构为每位提供一个输出，使得每个选定的存储单元被映射到n个输出，并且并行地读取存储在所选存储单元中的n位。 “按地址”架构提供每位一个地址，使得每个选定的存储单元被映射到一个输出，并且顺序地读取存储在所选存储单元中的n位。

6. 发明授权

US5796667A Bit map addressing schemes for flash memory 失效
公开(公告)号：US5796667A
公开(公告)日：1998-08-18
申请号：US639240
申请日：1996-04-19
申请人： Sherif Sweha , Mark E. Bauer
发明人： Sherif Sweha , Mark E. Bauer
IPC分类号： G11C16/06 , G11C8/00 , G11C11/56 , G11C16/02 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C2211/5631 , G11C2211/5632 , G11C2211/5642 , G11C8/00
摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

7. 发明授权

US5497354A Bit map addressing schemes for flash memory 失效
公开(公告)号：US5497354A
公开(公告)日：1996-03-05
申请号：US253902
申请日：1994-06-02
申请人： Sherif Sweha , Mark E. Bauer
发明人： Sherif Sweha , Mark E. Bauer
IPC分类号： G11C16/06 , G11C8/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C2211/5631 , G11C2211/5632 , G11C2211/5642 , G11C8/00
摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

8. 发明授权

US5274278A High-speed tri-level decoder with dual-voltage isolation 失效
标题翻译：具有双电压隔离的高速三电平解码器
公开(公告)号：US5274278A
公开(公告)日：1993-12-28
申请号：US816155
申请日：1991-12-31
申请人： Mark E. Bauer , Peter Hazen , Sherif Sweha
发明人： Mark E. Bauer , Peter Hazen , Sherif Sweha
IPC分类号： G11C17/00 , G11C8/10 , G11C8/12 , G11C16/06 , G11C16/08 , H03M5/16 , H03K19/20 , H03K19/082
CPC分类号： G11C16/08 , G11C8/10 , G11C8/12 , H03M5/16
摘要： In a memory array in which logic signals of a first and a second voltage levels are used for selecting memory positions in the array for read operations and at least one signal of a voltage level higher than the first and second voltage levels may appear, and including a plurality of wordlines each joined to a common node by individual row decoders, a predecoder circuit for selecting a plurality of wordlines from which a row decoder may select an individual wordline including a full CMOS NAND gate arranged to provide output voltage levels of the first and a second voltage levels, a plurality of weak P channel devices each connected to one of the wordlines, means for operating the weak P channel devices to provide voltage levels of the higher level and below at the wordlines, means for limiting value of voltage transferred to the common point to be less than the higher voltage level, and means for limiting the level of the voltage transferred to the common node from the NAND gate to be less than a predetermined level.
摘要翻译：在存储器阵列中，其中使用第一和第二电压电平的逻辑信号来选择用于读取操作的阵列中的存储器位置，并且可能出现高于第一和第二电压电平的电压电平的至少一个信号，并且包括多个字线，每个单独的行解码器连接到公共节点;预解码器电路，用于选择多个字线，行译码器可从该字线选择包括全CMOS NAND门的单独字线，布置成提供第一和第二电压电平，多个弱P沟道器件，每个连接到字线之一，用于操作弱P沟道器件以在字线处提供更高电平和更低电压电平的装置，用于限制转移到公共点小于较高的电压电平，以及用于将从NAND门转移到公共节点的电压的电平限制为小于预定水平。

9. 发明授权

US5245574A Apparatus for increasing the speed of operation of non-volatile memory arrays 失效
标题翻译：用于提高非易失性存储器阵列的操作速度的装置
公开(公告)号：US5245574A
公开(公告)日：1993-09-14
申请号：US812631
申请日：1991-12-23
申请人： Kevin W. Frary , George Canepa , Sherif Sweha
发明人： Kevin W. Frary , George Canepa , Sherif Sweha
IPC分类号： G11C7/12 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28
摘要： In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.
摘要翻译：在具有多个位线的存储器阵列中，每个位线连接到具有由存储器件传送电流的状态的多个存储器件以及该器件不传送电流的状态;列选择器件，用于激活每个位线，用于激活连接到每个位线的各个存储器件的多个字线，用于在连接到位线的存储器件的导通状态下提供恒定电流的设备，将源极电压连接到多个位线的器件以及用于提供输出参考信号，该改进包括用于提供电流源的装置，除了通过将源电压连接到多个位线的装置之外还提供电流源，以便当选择该位线时对所选位线的任何电容进行充电，从而在选择位线之间切换连接到不同位线的存储器件被加速。

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