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1. 发明授权

US5822256A Method and circuitry for usage of partially functional nonvolatile memory 失效
标题翻译：用于部分功能非易失性存储器的方法和电路
公开(公告)号：US5822256A
公开(公告)日：1998-10-13
申请号：US811194
申请日：1997-03-05
申请人： Mark E. Bauer , Steven Wells , David M. Brown , Johnny Javanifard , Sherif Sweha , Robert N. Hasbun , Gary J. Gallagher , Mamun Rashid , Rodney R. Rozman , Glen Hawk , George Blanchard , Mark Winston , Richard D. Pashley
发明人： Mark E. Bauer , Steven Wells , David M. Brown , Johnny Javanifard , Sherif Sweha , Robert N. Hasbun , Gary J. Gallagher , Mamun Rashid , Rodney R. Rozman , Glen Hawk , George Blanchard , Mark Winston , Richard D. Pashley
IPC分类号： G11C11/56 , G11C29/00 , G11C29/44 , G11C7/00
CPC分类号： G11C29/88 , G11C11/5621 , G11C11/5628 , G11C29/44 , G11C2211/5641
摘要： A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.
摘要翻译：描述了允许使用部分功能的集成电路存储器的方法和电路。存储器阵列被分离成单独的块，每个块可以被隔离以最小化由缺陷使得不可用的存储器阵列的量。还提供电路以将阵列内的存储器单元编程为至少三个电荷量之一，从而增加剩余功能块提供的存储量。

2. 发明授权

US5222046A Processor controlled command port architecture for flash memory 失效
标题翻译：闪存的处理器控制命令端口架构
公开(公告)号：US5222046A
公开(公告)日：1993-06-22
申请号：US601012
申请日：1990-10-19
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
IPC分类号： G11C16/16 , G11C16/32
CPC分类号： G11C16/16 , G11C16/32
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.
摘要翻译：一种半导体闪存EPROM / EEPROM器件，其包括命令端口控制器，用于从耦合到存储器件的数据总线接收命令指令。命令端口控制器的指令字用于指示设备执行读取，擦除，编程或验证功能，并且命令端口控制器产生必要的控制信号以使存储器正常工作。通过利用命令端口控制器，存储器件可以在器件在电路中被擦除和编程，并允许引脚与现有技术的EPROM和EEPROM兼容。

3. 发明授权

US5053990A Program/erase selection for flash memory 失效
标题翻译： FLASH存储器的程序/擦除选择
公开(公告)号：US5053990A
公开(公告)日：1991-10-01
申请号：US157361
申请日：1988-02-17
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
IPC分类号： G11C17/00 , G06F12/00 , G11C16/02 , G11C16/10 , G11C16/16 , G11C16/34 , G11C29/00 , G11C29/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/3459
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
摘要翻译：一种半导体闪存EPROM / EEPROM器件，包括用于在数据线上接收指令并向存储器提供控制信号以提供编程和擦除功能的命令端口，编程和擦除存储器的方法。程序序列包括在第一写周期期间设置程序命令，执行第二写周期以将地址寄存器加载到地址寄存器和数据到数据寄存器，在程序周期期间进行编程以及在第三写入期间写入程序验证命令写周期以在读周期中验证编程数据。擦除序列包括在第一写周期期间写入建立擦除命令，在擦除周期期间提供擦除的第二写周期期间的擦除命令，在第三写周期期间写入擦除验证命令，该第三写周期还解决存储器并在读周期期间提供擦除验证。擦除和编程周期都提供测量的增量擦除和编程。

4. 发明授权

US5490264A Generally-diagonal mapping of address space for row/column organizer memories 失效
标题翻译：行/列组织者存储器的地址空间的一般对角线映射
公开(公告)号：US5490264A
公开(公告)日：1996-02-06
申请号：US130023
申请日：1993-09-30
申请人： Steven Wells , Mark Winston
发明人： Steven Wells , Mark Winston
IPC分类号： G11C29/00 , G06F12/00
CPC分类号： G11C29/88
摘要： A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern. The arrangement allows the simplest forms of error detection and correction circuitry to be utilized.
摘要翻译：一种在闪存EEPROM阵列的块中以大致对角线图案存储数据的方法，由阵列导体或列导体的故障影响最少数量的存储器单元，以及用于寻址闪存阵列以产生这样的大致对角线的存储模式。该布置允许使用最简单的形式的错误检测和校正电路。

5. 发明授权

US5341330A Method for writing to a flash memory array during erase suspend intervals 失效
标题翻译：在擦除暂停间隔期间写入闪存阵列的方法
公开(公告)号：US5341330A
公开(公告)日：1994-08-23
申请号：US145732
申请日：1993-11-01
申请人： Steven E. Wells , Mark Winston , Virgil N. Kynett
发明人： Steven E. Wells , Mark Winston , Virgil N. Kynett
IPC分类号： G06F3/06 , G11C16/10 , G11C13/00
CPC分类号： G06F3/0601 , G11C16/102 , G06F2003/0694 , G06F2212/2022
摘要： A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.
摘要翻译：在数据的该部分被擦除和写入的时段期间，将数据写入快闪EEPROM存储器阵列的一部分中的条目的方法被禁止。该方法包括将数据写入除了正被擦除的阵列的部分之外的新的入口位置以及比阵列的原始部分中的原始数据的修订版本号大的修订版本号，写入忙原始条目到除了被擦除的阵列的部分之外的临时存储位置的条件，以及当擦除操作结束时使临时存储位置中列出的条目无效。

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