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1. 发明授权

US5532915A Method and apparatus for providing an ultra low power regulated negative charge pump 失效
标题翻译：提供超低功率调节负电荷泵的方法和装置
公开(公告)号：US5532915A
公开(公告)日：1996-07-02
申请号：US217095
申请日：1994-03-23
申请人： Dimitris Pantelakis , Kerry Tedrow , Johnny Javanifard , George Canepa
发明人： Dimitris Pantelakis , Kerry Tedrow , Johnny Javanifard , George Canepa
IPC分类号： G05F3/24 , G11C5/14 , G11C11/407 , G11C16/30 , H02M3/07 , H02M3/18 , G05F3/16
CPC分类号： H02M3/07 , G05F3/242 , G11C16/30 , G11C5/147
摘要： A circuit for providing a regulated output voltage from a charge pump circuit while utilizing very low amounts of power, the circuit including a clock circuit for providing clock pulses to operate the charge pump circuit to produce an output voltage, a bias circuit for monitoring the output voltage of the charge pump and furnishing signals for enabling the clock circuit in response to an insufficient output voltage, and circuitry for enabling the bias circuit during a fraction of the total operating time available to the charge pump.
摘要翻译：一种用于在利用非常低的功率的情况下从电荷泵电路提供稳定的输出电压的电路，所述电路包括用于提供时钟脉冲以操作电荷泵电路以产生输出电压的时钟电路，用于监视输出的偏置电路电荷泵的电压和提供用于响应于不足的输出电压的时钟电路的信号，以及用于在电荷泵可用的总操作时间的一小部分期间实现偏置电路的电路。

2. 发明授权

US5245574A Apparatus for increasing the speed of operation of non-volatile memory arrays 失效
标题翻译：用于提高非易失性存储器阵列的操作速度的装置
公开(公告)号：US5245574A
公开(公告)日：1993-09-14
申请号：US812631
申请日：1991-12-23
申请人： Kevin W. Frary , George Canepa , Sherif Sweha
发明人： Kevin W. Frary , George Canepa , Sherif Sweha
IPC分类号： G11C7/12 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28
摘要： In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.
摘要翻译：在具有多个位线的存储器阵列中，每个位线连接到具有由存储器件传送电流的状态的多个存储器件以及该器件不传送电流的状态;列选择器件，用于激活每个位线，用于激活连接到每个位线的各个存储器件的多个字线，用于在连接到位线的存储器件的导通状态下提供恒定电流的设备，将源极电压连接到多个位线的器件以及用于提供输出参考信号，该改进包括用于提供电流源的装置，除了通过将源电压连接到多个位线的装置之外还提供电流源，以便当选择该位线时对所选位线的任何电容进行充电，从而在选择位线之间切换连接到不同位线的存储器件被加速。

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