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1. 发明授权

US07696038B1 Methods for fabricating flash memory devices 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07696038B1
公开(公告)日：2010-04-13
申请号：US11412365
申请日：2006-04-26
申请人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
发明人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , G11C16/3418 , G11C16/3427
摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.
摘要翻译：提供了制造闪速存储器件的方法。根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。第一杂质掺杂区域形成在沟槽下面的衬底内。

2. 发明授权

US08076712B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
标题翻译：半导体存储器包括双电荷存储节点及其制造方法
公开(公告)号：US08076712B2
公开(公告)日：2011-12-13
申请号：US12840165
申请日：2010-07-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

3. 发明授权

US07767517B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
标题翻译：半导体存储器包括双电荷存储节点及其制造方法
公开(公告)号：US07767517B2
公开(公告)日：2010-08-03
申请号：US11613513
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L21/8242
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

4. 发明申请

US20080149999A1 SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION 有权
标题翻译：包含双电池存储器的半导体存储器及其制造方法
公开(公告)号：US20080149999A1
公开(公告)日：2008-06-26
申请号：US11613513
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

5. 发明授权

US07666739B2 Methods for fabricating a split charge storage node semiconductor memory 有权
标题翻译：分离电荷存储节点半导体存储器的制造方法
公开(公告)号：US07666739B2
公开(公告)日：2010-02-23
申请号：US11614048
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/792
摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.
摘要翻译：提供了用于制造分离电荷存储节点半导体存储器件的方法。根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极。栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构厚度。

6. 发明申请

US20080153222A1 METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR MEMORY 有权
标题翻译：用于制造分离充电储存节点半导体存储器的方法
公开(公告)号：US20080153222A1
公开(公告)日：2008-06-26
申请号：US11614048
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Sugimo Rinji , Wei Zheng
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/792
摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.
摘要翻译：提供了用于制造分离电荷存储节点半导体存储器件的方法。根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极。栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构厚度。

7. 发明授权

US07432156B1 Memory device and methods for its fabrication 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07432156B1
公开(公告)日：2008-10-07
申请号：US11409361
申请日：2006-04-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
摘要翻译：提供半导体存储器件及其制造方法。根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

8. 发明授权

US07564091B2 Memory device and methods for its fabrication 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07564091B2
公开(公告)日：2009-07-21
申请号：US12199692
申请日：2008-08-27
申请人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
发明人： Chungho Lee , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
摘要翻译：提供半导体存储器件及其制造方法。根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

9. 发明申请

US20080315290A1 MEMORY DEVICE AND METHODS FOR ITS FABRICATION 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080315290A1
公开(公告)日：2008-12-25
申请号：US12199692
申请日：2008-08-27
申请人： Chungho LEE , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
发明人： Chungho LEE , Ashot Melik-Martirosian , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Meng Ding
IPC分类号： H01L29/00
CPC分类号： H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
摘要翻译：提供半导体存储器件及其制造方法。根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

10. 发明授权

US08012830B2 ORO and ORPRO with bit line trench to suppress transport program disturb 有权
标题翻译： ORO和ORPRO与位线沟槽抑制传输程序干扰
公开(公告)号：US08012830B2
公开(公告)日：2011-09-06
申请号：US11835542
申请日：2007-08-08
申请人： Ning Cheng , Kuo-Tung Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
发明人： Ning Cheng , Kuo-Tung Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。存储单元包含电荷存储层和第一多晶硅栅极。位线开口延伸到半导体衬底中。通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

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