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1. 发明授权

US6054338A Low cost ball grid array device and method of manufacture thereof 失效
标题翻译：低成本球栅阵列装置及其制造方法
公开(公告)号：US6054338A
公开(公告)日：2000-04-25
申请号：US26781
申请日：1998-02-20
申请人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew , Hee Jhin Kim
发明人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew , Hee Jhin Kim
IPC分类号： H01L21/48 , H01L21/60 , H01L21/673 , H01L21/68 , H01L23/13 , H01L23/498 , H01L21/44 , H01L21/50
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/6835 , H01L23/13 , H01L24/32 , H01L24/86 , H01L2221/68313 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.
摘要翻译：选择例如双马来酰亚胺三嗪（BT）或陶瓷（Al 2 O 3）的面板大体上被最终结果的球栅阵列（BGA）装置充满和吸收。最终结果设备紧密地放置在一起并占据初始面板的整个区域。在面板中的适当位置提供结构弱化，以允许装置容易地分割。

2. 发明授权

US5783866A Low cost ball grid array device and method of manufacture thereof 失效
公开(公告)号：US5783866A
公开(公告)日：1998-07-21
申请号：US649395
申请日：1996-05-17
申请人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew , Hee Jhin Kim
发明人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew , Hee Jhin Kim
IPC分类号： H01L21/48 , H01L21/60 , H01L21/673 , H01L21/68 , H01L23/13 , H01L23/498 , H01L23/48 , H01L23/04 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/6835 , H01L23/13 , H01L24/32 , H01L24/86 , H01L2221/68313 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.

3. 发明授权

US06284566B1 Chip scale package and method for manufacture thereof 有权
标题翻译：芯片级封装及其制造方法
公开(公告)号：US06284566B1
公开(公告)日：2001-09-04
申请号：US09387170
申请日：1999-08-31
申请人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew
发明人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew
IPC分类号： H01L2144
CPC分类号： H01L21/4853 , H01L21/6835 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/86 , H01L2221/68313 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012 , H01L2224/45099
摘要： An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.
摘要翻译：组装过程提供了一种芯片级封装（CSP），其特征在于包括（i）穿孔基板，其中可以嵌入通孔，（ii）可以连接集成电路管芯的焊接掩模，以及（iii）有效利用用于将来自集成电路管芯的信号电气路由到连接到穿孔基板的外部端子的表面积。所得到的封装非常紧凑，因此具有比集成电路芯片的表面积更小的脚印。因此，基板和封装材料的成本最小化。组装过程允许非常高的批量生产，因为可以在衬底的单个单元上制造大量的集成电路，并且在组装过程中在比常规工艺中的相应阶段晚得多的阶段执行单个化。

4. 发明授权

US6140708A Chip scale package and method for manufacture thereof 失效
标题翻译：芯片级封装及其制造方法
公开(公告)号：US6140708A
公开(公告)日：2000-10-31
申请号：US889834
申请日：1997-07-08
申请人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew
发明人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew
IPC分类号： H01L21/48 , H01L21/60 , H01L21/673 , H01L21/68 , H01L23/13 , H01L23/498 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/86 , H01L21/4853 , H01L21/6835 , H01L23/13 , H01L23/49816 , H01L24/32 , H01L2221/68313 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/19042 , Y02P80/30
摘要： An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.
摘要翻译：组装过程提供了一种芯片级封装（CSP），其特征在于包括（i）穿孔基板，其中可以嵌入通孔，（ii）可以连接集成电路管芯的焊接掩模，以及（iii）有效利用用于将来自集成电路管芯的信号电气路由到连接到穿孔基板的外部端子的表面积。所得到的封装非常紧凑，因此具有比集成电路芯片的表面积更小的脚印。因此，基板和封装材料的成本最小化。组装过程允许非常高的批量生产，因为可以在衬底的单个单元上制造大量集成电路，并且在组装过程中在比常规工艺中的相应阶段晚得多的阶段执行单个化。

5. 发明授权

US06362530B1 Manufacturing methods and construction for integrated circuit packages 失效
标题翻译：集成电路封装的制造方法和结构
公开(公告)号：US06362530B1
公开(公告)日：2002-03-26
申请号：US09056074
申请日：1998-04-06
申请人： Shaw Wei Lee , Hem P. Takiar
发明人： Shaw Wei Lee , Hem P. Takiar
IPC分类号： H01L2348
CPC分类号： H01L23/49816 , H01L23/057 , H01L23/3675 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： A method of forming an integrated circuit package includes providing a flip chip integrating circuit die having a first plurality of contacts for electrically connecting the die to other elements. A second plurality of contacts for electrically connecting the integrated circuit package to external elements is also provided. A substrate for supporting the flip chip die and the second plurality of contacts is initially prepared. The substrate includes a connecting arrangement for electrically connecting the first plurality of contacts on the die to the second plurality of contacts. The method includes the step positioning the flip chip integrated circuit die and the second plurality of contacts on the substrate. With the flip chip die and the second plurality of contacts in position, both the first plurality of contacts on the flip chip die and the second plurality of contacts are simultaneously attached to the substrate thereby electrically connecting the die and the second plurality of contacts to the substrate. In one embodiment, a metal cap is attached to the integrated circuit package to cover and protect the die. In this embodiment, the metal cap may be used to provide a direct thermal path from the die to the external element to which the integrated circuit package is to the connected. An additional heat sink may also be attached to the package.
摘要翻译：形成集成电路封装的方法包括提供具有第一多个触点的倒装芯片集成电路管芯，用于将管芯电连接到其它元件。还提供了用于将集成电路封装电连接到外部元件的第二多个触点。最初准备了用于支撑倒装芯片模具和第二多个触点的基板。基板包括用于将模具上的第一多个触点电连接到第二多个触点的连接装置。该方法包括将倒装芯片集成电路管芯和第二多个触点定位在衬底上的步骤。通过倒装晶片管芯和第二组触头就位，倒装晶片管芯上的第一个多个触点和第二个多个触头都同时附着在基板上，从而将管芯和第二个多个触头电连接到基质。在一个实施例中，金属盖连接到集成电路封装以覆盖和保护管芯。在该实施例中，金属盖可用于提供从模具到集成电路封装件所连接的外部元件的直接热路径。附加的散热器也可以附接到包装上。

6. 发明授权

US06173490B1 Method for forming a panel of packaged integrated circuits 失效
标题翻译：用于形成封装集成电路板的方法
公开(公告)号：US06173490B1
公开(公告)日：2001-01-16
申请号：US08915352
申请日：1997-08-20
申请人： Shaw Wei Lee , Hem P. Takiar , Fred Drummond
发明人： Shaw Wei Lee , Hem P. Takiar , Fred Drummond
IPC分类号： H05K330
CPC分类号： H01L21/561 , B29C39/10 , B29C39/24 , H01L21/565 , H01L23/544 , H01L24/16 , H01L24/48 , H01L24/97 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2223/54486 , H01L2224/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/1517 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , Y10T29/49146 , Y10T29/49158 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： A method and an apparatus for forming a panel of packaged integrated circuits is disclosed. A substrate panel having an array of integrated circuits mounted thereon is placed in a mold having a molding chamber. The molding chamber has a multiplicity of adjacent package recesses flowably interconnected by way of a plurality of molding compound flowgates. Each package recess is suitable for receiving at least one associated integrated circuits. A molding compound is passed into the molding chamber by way of a mold gate such that at least some of the molding compound passes through a plurality of different package recesses by way of their associated flowgates. In one embodiment, the mold includes a mold body having a molding chamber with a plurality of ridges that define the multiplicity of package recesses within the molding chamber. The multiplicity of package recesses are flowably interconnected through flowgates formed by the ridges.
摘要翻译：公开了一种用于形成封装集成电路板的方法和装置。将具有安装在其上的集成电路阵列的基板面板放置在具有模制室的模具中。模制室具有多个相邻的包装凹部，其可通过多个模塑复合流动臂可流动地相互连接。每个封装凹槽适于接收至少一个相关联的集成电路。模塑料通过模具浇口进入模制室，使得至少一些模塑料通过其相关的流动浇口穿过多个不同的包装凹槽。在一个实施例中，模具包括具有模制室的模具主体，模制室具有限定模制室内的多个封装凹槽的多个脊。包装凹槽的多个可通过由脊形成的流动闸流动地相互连接。

7. 发明授权

US07846775B1 Universal lead frame for micro-array packages 有权
标题翻译：通用引线框架用于微阵列封装
公开(公告)号：US07846775B1
公开(公告)日：2010-12-07
申请号：US11135836
申请日：2005-05-23
申请人： Shaw Wei Lee , Nghia Thuc Tu , Sadanand R. Patil
发明人： Shaw Wei Lee , Nghia Thuc Tu , Sadanand R. Patil
IPC分类号： H01L21/00
CPC分类号： H01L21/4821 , H01L21/4828 , H01L21/4842 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/4951 , H01L23/49541 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/73265 , H01L2224/83101 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： Techniques for forming micro-array style packages are disclosed. A matrix of isolated contact posts are placed on an adhesive carrier. Dice are then mounted (directly or indirectly) on the carrier and each die is electrically connected to a plurality of associated contacts. The dice and portions of the contacts are then encapsulated in a manner that leaves at least bottom portions of the contacts exposed to facilitate electrical connection to external devices. The encapsulant serves to hold the contacts in place after the carrier has been removed.
摘要翻译：公开了用于形成微阵列风格包装的技术。将隔离的接触柱的矩阵放置在粘合剂载体上。然后将骰子（直接或间接地）安装在载体上，并且每个管芯电连接到多个相关的触点。然后，以使得触点的至少底部部分暴露以促进与外部装置的电连接的方式封装模具和部分触点。密封剂用于在移除载体之后将触点保持在适当的位置。

8. 发明授权

US07205095B1 Apparatus and method for packaging image sensing semiconductor chips 有权
标题翻译：用于封装图像感测半导体芯片的装置和方法
公开(公告)号：US07205095B1
公开(公告)日：2007-04-17
申请号：US10666921
申请日：2003-09-17
申请人： Ashok Prabhu , Shaw Wei Lee
发明人： Ashok Prabhu , Shaw Wei Lee
IPC分类号： G03C5/00 , H01L31/0203
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： An method and apparatus for fabricating a die having imaging circuitry and fabricating a lid having a transparent region and support regions having a predetermined height. The lid is fabricated by applying a photo-sensitive adhesive layer with a thickness substantially equal to the predetermined height to a transparent plate and patterning the photo-sensitive adhesive layer to form the transparent region and the support regions. Once fabrication of the lid is complete, it is mounted directly onto the die so that the transparent region generally covers the imaging circuitry. The resulting apparatus includes a lid mounted directly onto the die with the transparent region generally positioned above the imaging circuitry. A gap, having a height dimension substantially equal to the predetermined height of the support regions of the lid, is spaced between the transparent region of the lid and the imaging circuitry on the die.
摘要翻译：一种用于制造具有成像电路并具有透明区域的盖子和具有预定高度的支撑区域的模具的方法和装置。通过将具有基本上等于预定高度的厚度的光敏粘合剂层施加到透明板并图案化光敏粘合剂层以形成透明区域和支撑区域来制造盖。一旦盖的制造完成，就将其直接安装在模具上，使得透明区域通常覆盖成像电路。所得到的装置包括直接安装在模具上的盖，透明区域通常位于成像电路的上方。具有基本上等于盖的支撑区域的预定高度的高度尺寸的间隙在盖的透明区域和模具上的成像电路之间间隔开。

9. 发明授权

US5686842A Known good die test apparatus and method 失效
标题翻译：已知的好的模具试验装置和方法
公开(公告)号：US5686842A
公开(公告)日：1997-11-11
申请号：US521619
申请日：1995-08-31
申请人： Shaw Wei Lee
发明人： Shaw Wei Lee
IPC分类号： G01R1/073
CPC分类号： G01R1/07357
摘要： An apparatus and method for testing an integrated circuit chip prior to mounting on a package including a non-conductive tape upon which are formed a plurality of contacts arranged in a pattern matching the arrangement of bonding pads of an integrated circuit, and a z-axis conductor placed over the conductive tape. The target chip is placed on the z-axis conductor and test signals are transmitted between the contacts on the tape and the bonding pads of the integrated circuit through conductors embedded in the z-axis conductor. In one embodiment, a glass or ceramic plate including openings, arranged in the same pattern as the bonding pads, is placed between the integrated circuit and the z-axis conductor to prevent damage to the integrated circuit.
摘要翻译：一种用于在安装在包括非导电胶带的包装上的集成电路芯片测试的装置和方法，在该封装上形成多个以与集成电路的接合焊盘的布置匹配的图案布置的触点，以及z轴导体放置在导电胶带上。目标芯片放置在z轴导体上，测试信号通过嵌入在z轴导体中的导体在磁带上的触点和集成电路的焊盘之间传输。在一个实施例中，包括以与接合焊盘相同的图案的开口的玻璃或陶瓷板被放置在集成电路和z轴导体之间，以防止对集成电路的损坏。

10. 发明授权

US07087986B1 Solder pad configuration for use in a micro-array integrated circuit package 有权
标题翻译：焊盘配置用于微阵列集成电路封装
公开(公告)号：US07087986B1
公开(公告)日：2006-08-08
申请号：US10871313
申请日：2004-06-18
申请人： Jaime A. Bayan , Ashok S. Prabhu , Shaw Wei Lee
发明人： Jaime A. Bayan , Ashok S. Prabhu , Shaw Wei Lee
IPC分类号： H01L23/495 , H01L23/04
CPC分类号： H01L23/49541 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48463 , H01L2224/48465 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A solder pad configuration for use in an IC package is described. Various embodiments of the invention describe IC packages, lead-frames, or substrate panels configured with generally noncircular solder pads at their bottom surfaces. The noncircular shapes allow for greater surface area than circular solder pads having diameters equal to a major dimension of the noncircular shapes, while maintaining the same metal-to-metal clearance between the pads and adjacent leads. This increased surface area provides for stronger and more reliable solder joints.
摘要翻译：描述了用于IC封装中的焊盘配置。本发明的各种实施例描述了在其底表面上配置有大致非圆形焊盘的IC封装，引线框架或基板。非圆形形状允许比具有等于非圆形形状的主要尺寸的直径的圆形焊盘更大的表面积，同时在焊盘和相邻引线之间保持相同的金属与金属间隙。这种增加的表面积提供了更坚固和更可靠的焊点。

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