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1. 发明授权

US06224737B1 Method for improvement of gap filling capability of electrochemical deposition of copper 有权
标题翻译：改进铜电化学沉积间隙填充能力的方法
公开(公告)号：US06224737B1
公开(公告)日：2001-05-01
申请号：US09377540
申请日：1999-08-19
申请人： Ming-Hsing Tsai , Wen-Jye Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Wen-Jye Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： C25D502
CPC分类号： H01L21/76877 , C25D3/38 , C25D5/48 , C25D7/123 , H01L21/2885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.
摘要翻译：提供具有形成在其中的沟槽的半导体结构。半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。

2. 发明授权

US6140241A Multi-step electrochemical copper deposition process with improved filling capability 有权
标题翻译：多步电化学铜沉积工艺具有改善的填充能力
公开(公告)号：US6140241A
公开(公告)日：2000-10-31
申请号：US270591
申请日：1999-03-18
申请人： Shau-Lin Shue , Ming-Hsing Tsai , Wen-Jye Tsai , Chen-Hua Yu
发明人： Shau-Lin Shue , Ming-Hsing Tsai , Wen-Jye Tsai , Chen-Hua Yu
IPC分类号： H01L21/288 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76877 , H01L21/2885
摘要： A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the contact/vias are filled and additional copper is deposited over them at a high deposition rate. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.
摘要翻译：描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。该方法设计为通过在两个沉积阶段之间执行铜的电化学沉积，具有阶段之间的停留时间，以提供良好的覆盖和间隙填充能力以及高的生产量。该方法使用含有添加的增白剂和矫直机的镀铜电解质。第一次沉积以低电流密度进行，这提供了由高投掷功率引起的良好覆盖。高长宽比的接触/通孔开口用相当厚度的均匀的高质量铜涂层覆盖。在沉积期间，增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。增亮剂的浓度，在电镀电流停止的短暂停留期间通过扩散在这些区域补充。接下来，施加高电流密度，由此接触/通孔被填充，并且以高沉积速率在其上沉积额外的铜。通过高电流密度步骤，当该方法应用于双镶嵌冶金的形成时，实现了最大的生产效率。

3. 发明授权

US06620725B1 Reduction of Cu line damage by two-step CMP 有权
标题翻译：通过两步CMP减少Cu线损伤
公开(公告)号：US06620725B1
公开(公告)日：2003-09-16
申请号：US09395287
申请日：1999-09-13
申请人： Shau-Lin Shue , Ming-Hsing Tsai , Wen-Jye Tsai , Ying-Ho Chen , Tsu Shih , Jih-Churng Twu , Syun-Ming Jang
发明人： Shau-Lin Shue , Ming-Hsing Tsai , Wen-Jye Tsai , Ying-Ho Chen , Tsu Shih , Jih-Churng Twu , Syun-Ming Jang
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.
摘要翻译：描述用于在两个步骤中执行CMP的过程。在沟槽已经形成并且用铜过度填充之后，在本发明的第一实施例中，最初使用硬焊盘去除大部分铜，直到达到一个点，其中凹陷效应将开始出现。然后取代软焊盘，继续CMP直到除了沟槽中除去所有的铜。在第二实施例中，使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。如前所述，使用这种组合，直到达到点，其中凹陷效应将开始出现。然后，除了沟槽之外，使用相对较低的压力结合相对高的转速直到除去所有的铜。这两个实施例都导致刚好填充铜的沟槽，几乎没有凹陷效应，并且除了沟槽本身之外，所有痕迹的铜都被去除。

4. 发明授权

US06562725B2 Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers 有权
标题翻译：采用氮化碳化硅和非氮化碳化硅蚀刻停止层的双镶嵌结构
公开(公告)号：US06562725B2
公开(公告)日：2003-05-13
申请号：US09899420
申请日：2001-07-05
申请人： Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2100
CPC分类号： H01L21/76829 , H01L21/31116 , H01L21/314 , H01L21/7681 , H01L21/76834
摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.
摘要翻译：在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

5. 发明申请

US20050170648A1 Method to solve via poisoning for porous low-k dielectric 有权
公开(公告)号：US20050170648A1
公开(公告)日：2005-08-04
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

6. 发明授权

US07354856B2 Method for forming dual damascene structures with tapered via portions and improved performance 有权
标题翻译：用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
公开(公告)号：US07354856B2
公开(公告)日：2008-04-08
申请号：US11071104
申请日：2005-03-04
申请人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/314 , H01L21/76808 , Y10S438/978
摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
摘要翻译：提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。在一个实施例中，具有导电层的衬底形成在第一绝缘层中。在导电层上形成保护层。在保护层和第一绝缘层上方形成蚀刻停止层。在蚀刻停止层上形成第二绝缘层。第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。通孔塞至少部分地填充在第一开口中。在第二绝缘层上方形成抗反射涂层（ARC）层。第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

7. 发明授权

US07250683B2 Method to solve via poisoning for porous low-k dielectric 有权
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US07250683B2
公开(公告)日：2007-07-31
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

8. 发明申请

US20060199379A1 Method for forming dual damascene structures with tapered via portions and improved performance 有权
标题翻译：用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
公开(公告)号：US20060199379A1
公开(公告)日：2006-09-07
申请号：US11071104
申请日：2005-03-04
申请人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/4763 , H01L21/31
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/314 , H01L21/76808 , Y10S438/978
摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
摘要翻译：提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。在一个实施例中，具有导电层的衬底形成在第一绝缘层中。在导电层上形成保护层。在保护层和第一绝缘层上方形成蚀刻停止层。在蚀刻停止层上形成第二绝缘层。第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。通孔插塞至少部分地填充在第一开口中。在第二绝缘层上方形成抗反射涂层（ARC）层。第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

9. 发明授权

US06878615B2 Method to solve via poisoning for porous low-k dielectric 失效
标题翻译：解决多孔低介电常数中毒的方法
公开(公告)号：US06878615B2
公开(公告)日：2005-04-12
申请号：US09863224
申请日：2001-05-24
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.
摘要翻译：公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

10. 发明授权

US06759750B2 Method for integrating low-K materials in semiconductor fabrication 失效
标题翻译：半导体制造中低K材料的集成方法
公开(公告)号：US06759750B2
公开(公告)日：2004-07-06
申请号：US10623910
申请日：2003-07-18
申请人： Shau-Lin Shue , Ming-Hsing Tsai
发明人： Shau-Lin Shue , Ming-Hsing Tsai
IPC分类号： H01L2348
CPC分类号： H01L23/522 , H01L21/76801 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.
摘要翻译：一种用于在半导体制造中集成低K材料的方法。该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。图案化电介质层以形成柱状开口。在半导体结构上沉积柱层; 从而用柱层填充柱状开口。柱层被平坦化以形成嵌入在所述介电层中的柱。柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。在一个实施例中，在形成双镶嵌层间接触之前形成柱。在另一个实施方案中，柱与层间接触同时形成。

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