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    • 1. 发明授权
    • Reduction of Cu line damage by two-step CMP
    • 通过两步CMP减少Cu线损伤
    • US06620725B1
    • 2003-09-16
    • US09395287
    • 1999-09-13
    • Shau-Lin ShueMing-Hsing TsaiWen-Jye TsaiYing-Ho ChenTsu ShihJih-Churng TwuSyun-Ming Jang
    • Shau-Lin ShueMing-Hsing TsaiWen-Jye TsaiYing-Ho ChenTsu ShihJih-Churng TwuSyun-Ming Jang
    • H01L214763
    • H01L21/7684H01L21/3212
    • A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.
    • 描述用于在两个步骤中执行CMP的过程。 在沟槽已经形成并且用铜过度填充之后,在本发明的第一实施例中,最初使用硬焊盘去除大部分铜,直到达到一个点,其中凹陷效应将开始出现。 然后取代软焊盘,继续CMP直到除了沟槽中除去所有的铜。 在第二实施例中,使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。 如前所述,使用这种组合,直到达到点,其中凹陷效应将开始出现。 然后,除了沟槽之外,使用相对较低的压力结合相对高的转速直到除去所有的铜。 这两个实施例都导致刚好填充铜的沟槽,几乎没有凹陷效应,并且除了沟槽本身之外,所有痕迹的铜都被去除。
    • 2. 发明授权
    • Multi-step electrochemical copper deposition process with improved
filling capability
    • 多步电化学铜沉积工艺具有改善的填充能力
    • US6140241A
    • 2000-10-31
    • US270591
    • 1999-03-18
    • Shau-Lin ShueMing-Hsing TsaiWen-Jye TsaiChen-Hua Yu
    • Shau-Lin ShueMing-Hsing TsaiWen-Jye TsaiChen-Hua Yu
    • H01L21/288H01L21/768H01L21/302H01L21/461
    • H01L21/76877H01L21/2885
    • A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the contact/vias are filled and additional copper is deposited over them at a high deposition rate. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.
    • 描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。 该方法设计为通过在两个沉积阶段之间执行铜的电化学沉积,具有阶段之间的停留时间,以提供良好的覆盖和间隙填充能力以及高的生产量。 该方法使用含有添加的增白剂和矫直机的镀铜电解质。 第一次沉积以低电流密度进行,这提供了由高投掷功率引起的良好覆盖。 高长宽比的接触/通孔开口用相当厚度的均匀的高质量铜涂层覆盖。 在沉积期间,增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。 增亮剂的浓度,在电镀电流停止的短暂停留期间通过扩散在这些区域补充。 接下来,施加高电流密度,由此接触/通孔被填充,并且以高沉积速率在其上沉积额外的铜。 通过高电流密度步骤,当该方法应用于双镶嵌冶金的形成时,实现了最大的生产效率。
    • 3. 发明授权
    • Method for improvement of gap filling capability of electrochemical deposition of copper
    • 改进铜电化学沉积间隙填充能力的方法
    • US06224737B1
    • 2001-05-01
    • US09377540
    • 1999-08-19
    • Ming-Hsing TsaiWen-Jye TsaiShau-Lin ShueChen-Hua Yu
    • Ming-Hsing TsaiWen-Jye TsaiShau-Lin ShueChen-Hua Yu
    • C25D502
    • H01L21/76877C25D3/38C25D5/48C25D7/123H01L21/2885H01L23/53238H01L2924/0002H01L2924/00
    • A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.
    • 提供具有形成在其中的沟槽的半导体结构。 半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。 电压被施加到沟槽半导体,其诱导偏置场,其中存在靠近沟槽底部的第一场和大于第一场,接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。 将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。 由于感应偏压场,光滑剂浓度在沟槽底部附近较大,并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。 然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内,并且覆盖填充半导体结构的上表面。 然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。
    • 4. 发明授权
    • Gap filling by two-step plating
    • 间隙填充通过两步电镀
    • US06319831B1
    • 2001-11-20
    • US09507904
    • 2000-02-22
    • Wen-Jye TsaiMing-Hsing Tsai
    • Wen-Jye TsaiMing-Hsing Tsai
    • H01L2144
    • H01L21/2885H01L21/76877
    • A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by depositing the copper in two stages with an optional dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brighteners and levelers. A first copper layer is plated at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio openings are covered with a substantial thickness of a uniform, high quality copper coating. During plating, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. Optionally, the brightener is replenished in these regions during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the openings are filled and additional copper is deposited over them at a high deposition rate. A benefit of the high current density deposition is that depletion of leveler chemical in the openings enhances the growth rate of copper at the base of the openings thereby favoring growth from bottom up. This avoids the formation of voids in the openings. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.
    • 描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。 该方法设计为通过在两个阶段之间以可选的停留时间两段沉积铜来提供良好的覆盖和间隙填充能力以及高的生产量。 该方法使用含有添加的增白剂和矫光剂的镀铜电解质。 第一铜层以低电流密度电镀,由高投掷功率提供良好的覆盖。 高长宽比的开口用相当厚度的均匀的高质量铜涂层覆盖。 在电镀期间,增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。 任选地,在电镀电流停止的短暂停留期间,增白剂在这些区域中补充。 接下来,施加高电流密度,由此填充开口并且以高沉积速率在其上沉积附加的铜。 高电流密度沉积的益处在于开口中矫正剂化学品的消耗增加了开口底部的铜的生长速率,从而有利于从下到上生长。 这避免了在开口中形成空隙。 通过高电流密度步骤,当该方法应用于双镶嵌冶金的形成时,实现了最大的生产效率。