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1. 发明授权

US06920621B1 Methods of testing for shorts in programmable logic devices using relative quiescent current measurements 有权
标题翻译：使用相对静态电流测量测试可编程逻辑器件中短路的方法
公开(公告)号：US06920621B1
公开(公告)日：2005-07-19
申请号：US10644158
申请日：2003-08-20
申请人： Shahin Toutounchi , Erik V. Chmelar , Robert W. Wells
发明人： Shahin Toutounchi , Erik V. Chmelar , Robert W. Wells
IPC分类号： G01R31/30 , G06F11/24 , G06F17/50
CPC分类号： G06F11/24 , G01R31/3008 , G06F17/5027
摘要： Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.
摘要翻译：测试集成电路中的互连线之间的短路（例如桥接缺陷）的方法。例如，在可编程逻辑器件（PLD）中实现的设计中，使用一些互连线，而其他互连线未被使用。为了测试使用和未使用的互连线之间的短路，使用的和未使用的互连线都被驱动到第一逻辑电平，并且测量泄漏电流。所使用的互连线被驱动到第二逻辑电平，而未使用的线保持在第一逻辑电平。再次测量电流，并确定两次测量之间的差异。如果差异超过预定阈值，则设备组合被拒绝。一些实施例提供了用于针对部分有缺陷的PLD的设计的在使用的和未使用的互连线之间的短路的测试方法。

2. 发明申请

US20130243071A1 PREDICTIVE SELECTION IN A FULLY UNROLLED DECISION FEEDBACK EQUALIZER 有权
标题翻译：全面的决策反馈平均预测选择
公开(公告)号：US20130243071A1
公开(公告)日：2013-09-19
申请号：US13422450
申请日：2012-03-16
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/063 , H04L2025/03496
摘要： Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators, each comparator provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit history. The predictive DFE includes a set of interleave groups, each interleave group having j interleaves. Each interleave determines a bit value of a corresponding sample in a window of samples. Each tap corresponds to a feedback path between adjacent interleave groups. Multiplexing logic of each interleave predictively selects a bit value of an associated tap based on a value of a corresponding select line in a previous interleave, thereby alleviating a unit interval timing constraint.
摘要翻译：所描述的实施例提供了用于产生接收信号的每个样本的值的非均匀量化的模数转换器（ADC）。 ADC包括决策比较器阵列，每个比较器提供接收信号。每个比较器具有根据预测判决反馈均衡器（DFE）的相应位历史设置的阈值电压，并且每个位历史与DFE的抽头相关联。每个比较器根据相应的位历史提供一个位值。预测DFE包括一组交织组，每个交织组具有j个交织。每个交错确定样本窗口中相应样本的位值。每个抽头对应于相邻交错组之间的反馈路径。每个交织的复用逻辑基于先前交织中的对应选择行的值来预测性地选择关联抽头的比特值，从而减轻单位间隔时间约束。

3. 发明授权

US08929497B2 Dynamic deskew for bang-bang timing recovery in a communication system 有权
标题翻译：在通信系统中进行颠簸定时恢复的动态偏移校正
公开(公告)号：US08929497B2
公开(公告)日：2015-01-06
申请号：US13422329
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/033 , H04L25/03057 , H04L2025/03363
摘要： Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled that iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin and voltage, the margin phase detector determines whether the sample phase is correct.
摘要翻译：描述的实施例校准接收机的采样相位调整。模拟 - 数字转换器在采样阶段产生接收信号的采样。相位检测器选择n个样本的窗口。如果窗口包括奈奎斯特图案，则对于奈奎斯特图案中的第一连续位和第二连续位之间的每个转换，迭代地启用爆炸阱，对接收信号在第一和第二连续的零交叉处进行采样位并确定转换极性。基于过渡极性和零交叉采样值，轰击陷阱确定采样相位是否正确。如果窗口中不存在奈奎斯特图案，则边缘相位检测器确定窗口的目标电压余量值和光标位的电压。基于目标电压余量和电压，边沿相位检测器确定采样相位是否正确。

4. 发明授权

US08615062B2 Adaptation using error signature analysis in a communication system 有权
标题翻译：在通信系统中使用错误签名分析进行适配
公开(公告)号：US08615062B2
公开(公告)日：2013-12-24
申请号：US13368315
申请日：2012-02-07
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： H04B1/10
CPC分类号： H04L25/03057
摘要： Described embodiments provide method of adapting pulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and, for the window, estimates a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of pre-cursor estimated bits, the estimated cursor bit, and a number of post-cursor estimated bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value. Based on the error signature value and a minimum pulse response value, it is determined whether the cursor bit corresponds to residual inter-symbol interference (ISI), and, if so, the error signature value is accumulated and tap values for each pulse response tap are adapted.
摘要翻译：描述的实施例提供了适配接收机的脉冲响应抽头的方法。模数转换器（ADC）为接收信号的每个位采样产生一个ADC值。错误签名分析（ESA）模块定义了位样本窗口，并且对于窗口，基于ADC值估计与每个采样相对应的位值。 ESA模块基于预先估计的比特数，所估计的光标位和一定数量的游标后估计位产生（i）对应于估计的光标位的重建ADC值，以及（ii）错误签名基于重建的ADC值和ADC值。基于错误签名值和最小脉冲响应值，确定光标位是否对应于残余符号间干扰（ISI），如果是，则累积误差签名值，并且每个脉冲响应抽头的抽头值适应。

5. 发明申请

US20130243070A1 TAP ADAPTATION WITH A FULLY UNROLLED DECISION FEEDBACK EQUALIZER 有权
标题翻译： TAP适应与一个完全不必要的决定反馈均衡器
公开(公告)号：US20130243070A1
公开(公告)日：2013-09-19
申请号：US13422403
申请日：2012-03-16
申请人： Choshu Ito , Erik V. Chmelar
发明人： Choshu Ito , Erik V. Chmelar
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L25/03057 , H04L2025/03687 , H04L2025/037
摘要： Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.
摘要翻译：描述的实施例通过将一个或多个数据恢复比较器中的每一个的参考电压设置为相应的预定初始值来适配接收机的判决反馈均衡器的一个或多个抽头。数据恢复比较器为接收信号的每个采样产生一个位值。接收机的抽头适配模块选择n个接收位样本的窗口。对于一个或多个数据恢复比较器中的每一个，迭代地分接自适应模块，跟踪（i）具有逻辑0值的检测到的比特数，以及（ii）具有逻辑1值的检测到的比特数。抽头适配模块基于检测到的具有逻辑0值的位数与检测到的具有逻辑1值的位数的比率，将相应数据恢复比较器的参考电压调整预定步长量。

6. 发明申请

US20130243107A1 BAUD RATE TIMING RECOVERY FOR NYQUIST PATTERNS IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：通信系统中NYQUIC模式的波特率时间恢复
公开(公告)号：US20130243107A1
公开(公告)日：2013-09-19
申请号：US13422259
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/06 , H04L27/04
CPC分类号： H04L7/033 , H04L7/046 , H04L25/03057
摘要： Described embodiments recover timing data from a received signal. An analog-to-digital converter (ADC) generates a value for each sample of the signal at a sample phase. A phase detector selects a window of n received bit samples, where n is a positive integer. If the bit window includes any Nyquist patterns, the phase detector enables a bang-bang trap. The bang-bang-trap iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the Nyquist patterns, samples the received signal at a zero crossing between the first and second consecutive bits and determines the polarity of the bit transition. Based on the polarity of the bit transition and the sample value at the zero crossing, the bang-bang trap determines whether the sample phase of the bit sample for the second consecutive bit is correct. If the sample phase is incorrect, the bang-bang trap adjusts the sample phase.
摘要翻译：所描述的实施例从接收到的信号中恢复定时数据。模拟数字转换器（ADC）在样本阶段产生每个信号样本的值。相位检测器选择n个接收位样本的窗口，其中n是正整数。如果位窗口包括任何奈奎斯特图案，则相位检测器能够进行爆炸陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个位转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定位转换的极性。基于位过渡的极性和过零点处的采样值，爆炸阱确定第二个连续位的位采样的采样相位是否正确。如果样品相不正确，则爆炸阱会调整样品相。

7. 发明申请

US20090243792A1 PROCESS VARIATION BASED MICROCHIP IDENTIFICATION 有权
标题翻译：基于过程变化的微机鉴定
公开(公告)号：US20090243792A1
公开(公告)日：2009-10-01
申请号：US12059040
申请日：2008-03-31
申请人： Erik V. Chmelar
发明人： Erik V. Chmelar
IPC分类号： G06F7/04
CPC分类号： G06F7/588 , H04L9/0861
摘要： An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.
摘要翻译：一种装置，包括多路复用器电路，多个位产生电路和控制电路。多路复用器电路可以被配置为响应于（i）多个输入比特和（ii）控制信号而产生中间信号。多个位产生电路可以各自被配置为生成多个输入位之一。控制电路可以被配置为产生控制信号。

8. 发明授权

US08923382B2 Tap adaptation with a fully unrolled decision feedback equalizer 有权
标题翻译：点击适应与完全展开的决策反馈均衡器
公开(公告)号：US08923382B2
公开(公告)日：2014-12-30
申请号：US13422403
申请日：2012-03-16
申请人： Choshu Ito , Erik V. Chmelar
发明人： Choshu Ito , Erik V. Chmelar
IPC分类号： H04L25/03
CPC分类号： H04L27/01 , H04L25/03057 , H04L2025/03687 , H04L2025/037
摘要： Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.
摘要翻译：描述的实施例通过将一个或多个数据恢复比较器中的每一个的参考电压设置为相应的预定初始值来适配接收机的判决反馈均衡器的一个或多个抽头。数据恢复比较器为接收信号的每个采样产生一个位值。接收机的抽头适配模块选择n个接收位样本的窗口。对于一个或多个数据恢复比较器中的每一个，迭代地分接自适应模块，跟踪（i）具有逻辑0值的检测到的比特数，以及（ii）具有逻辑1值的检测到的比特数。抽头适配模块基于检测到的具有逻辑0值的位数与检测到的具有逻辑1值的位数的比率，将相应数据恢复比较器的参考电压调整预定步长量。

9. 发明申请

US20130243127A1 DYNAMIC DESKEW FOR BANG-BANG TIMING RECOVERY IN A COMMUNICATION SYSTEM 有权
标题翻译：用于通信系统中的BANG-BANG定时恢复的动态DESKEW
公开(公告)号：US20130243127A1
公开(公告)日：2013-09-19
申请号：US13422329
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H04L25/03057 , H04L2025/03363
摘要： Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled. The bang-bang trap iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin value and the voltage of the cursor bit, the margin phase detector determines whether the sample phase is correct.
摘要翻译：描述的实施例校准接收机的采样相位调整。模拟 - 数字转换器在采样阶段产生接收信号的采样。相位检测器选择n个样本的窗口。如果窗口包含奈奎斯特（Nyquist）模式，则会启用“爆炸”陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定转换极性。基于过渡极性和零交叉采样值，轰击陷阱确定采样相位是否正确。如果窗口中不存在奈奎斯特图案，则边缘相位检测器确定窗口的目标电压余量值和光标位的电压。基于目标电压余量值和光标位电压，边缘相位检测器确定采样相位是否正确。

10. 发明申请

US20130243056A1 VOLTAGE MARGIN BASED BAUD RATE TIMING RECOVERY IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：基于电压基准的波特率通信系统中的时钟恢复
公开(公告)号：US20130243056A1
公开(公告)日：2013-09-19
申请号：US13422226
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04B1/06 , H04B1/02 , H04B17/00
CPC分类号： H04L7/033
摘要： Described embodiments provide a method of recovering timing data from a received signal. An analog-to-digital converter (ADC) of a receiver generates an actual ADC value for each bit sample of a received signal. Each bit sample occurs at an associated sample phase of the receiver. A margin phase detector of the receiver recovers timing information from the received signal by determining a target voltage margin value. The margin phase detector selects a window of n received bit samples, where n is a positive integer, and determines a voltage of a cursor bit of the selected window of bit samples. The margin phase detector determines, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct. If the sample phase is incorrect, the margin phase detector adjusts the sample phase of the receiver by a predetermined amount.
摘要翻译：描述的实施例提供了一种从接收信号中恢复定时数据的方法。接收机的模数转换器（ADC）为接收信号的每个位采样产生实际的ADC值。每个位采样发生在接收器的相关采样相位。接收器的边沿相位检测器通过确定目标电压余量值来从接收信号中恢复定时信息。边缘相位检测器选择n个接收位样本的窗口，其中n是正整数，并且确定所选择的位采样窗口的光标位的电压。边缘相位检测器基于目标电压余量值和光标位的电压来确定采样相位是否正确。如果采样相位不正确，则边沿相位检测器将接收器的采样相位调整预定量。

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