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1. 发明授权

US08929497B2 Dynamic deskew for bang-bang timing recovery in a communication system 有权
标题翻译：在通信系统中进行颠簸定时恢复的动态偏移校正
公开(公告)号：US08929497B2
公开(公告)日：2015-01-06
申请号：US13422329
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/033 , H04L25/03057 , H04L2025/03363
摘要： Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled that iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin and voltage, the margin phase detector determines whether the sample phase is correct.
摘要翻译：描述的实施例校准接收机的采样相位调整。模拟 - 数字转换器在采样阶段产生接收信号的采样。相位检测器选择n个样本的窗口。如果窗口包括奈奎斯特图案，则对于奈奎斯特图案中的第一连续位和第二连续位之间的每个转换，迭代地启用爆炸阱，对接收信号在第一和第二连续的零交叉处进行采样位并确定转换极性。基于过渡极性和零交叉采样值，轰击陷阱确定采样相位是否正确。如果窗口中不存在奈奎斯特图案，则边缘相位检测器确定窗口的目标电压余量值和光标位的电压。基于目标电压余量和电压，边沿相位检测器确定采样相位是否正确。

2. 发明申请

US20130243070A1 TAP ADAPTATION WITH A FULLY UNROLLED DECISION FEEDBACK EQUALIZER 有权
标题翻译： TAP适应与一个完全不必要的决定反馈均衡器
公开(公告)号：US20130243070A1
公开(公告)日：2013-09-19
申请号：US13422403
申请日：2012-03-16
申请人： Choshu Ito , Erik V. Chmelar
发明人： Choshu Ito , Erik V. Chmelar
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L25/03057 , H04L2025/03687 , H04L2025/037
摘要： Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.
摘要翻译：描述的实施例通过将一个或多个数据恢复比较器中的每一个的参考电压设置为相应的预定初始值来适配接收机的判决反馈均衡器的一个或多个抽头。数据恢复比较器为接收信号的每个采样产生一个位值。接收机的抽头适配模块选择n个接收位样本的窗口。对于一个或多个数据恢复比较器中的每一个，迭代地分接自适应模块，跟踪（i）具有逻辑0值的检测到的比特数，以及（ii）具有逻辑1值的检测到的比特数。抽头适配模块基于检测到的具有逻辑0值的位数与检测到的具有逻辑1值的位数的比率，将相应数据恢复比较器的参考电压调整预定步长量。

3. 发明申请

US20130243107A1 BAUD RATE TIMING RECOVERY FOR NYQUIST PATTERNS IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：通信系统中NYQUIC模式的波特率时间恢复
公开(公告)号：US20130243107A1
公开(公告)日：2013-09-19
申请号：US13422259
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/06 , H04L27/04
CPC分类号： H04L7/033 , H04L7/046 , H04L25/03057
摘要： Described embodiments recover timing data from a received signal. An analog-to-digital converter (ADC) generates a value for each sample of the signal at a sample phase. A phase detector selects a window of n received bit samples, where n is a positive integer. If the bit window includes any Nyquist patterns, the phase detector enables a bang-bang trap. The bang-bang-trap iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the Nyquist patterns, samples the received signal at a zero crossing between the first and second consecutive bits and determines the polarity of the bit transition. Based on the polarity of the bit transition and the sample value at the zero crossing, the bang-bang trap determines whether the sample phase of the bit sample for the second consecutive bit is correct. If the sample phase is incorrect, the bang-bang trap adjusts the sample phase.
摘要翻译：所描述的实施例从接收到的信号中恢复定时数据。模拟数字转换器（ADC）在样本阶段产生每个信号样本的值。相位检测器选择n个接收位样本的窗口，其中n是正整数。如果位窗口包括任何奈奎斯特图案，则相位检测器能够进行爆炸陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个位转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定位转换的极性。基于位过渡的极性和过零点处的采样值，爆炸阱确定第二个连续位的位采样的采样相位是否正确。如果样品相不正确，则爆炸阱会调整样品相。

4. 发明授权

US08923382B2 Tap adaptation with a fully unrolled decision feedback equalizer 有权
标题翻译：点击适应与完全展开的决策反馈均衡器
公开(公告)号：US08923382B2
公开(公告)日：2014-12-30
申请号：US13422403
申请日：2012-03-16
申请人： Choshu Ito , Erik V. Chmelar
发明人： Choshu Ito , Erik V. Chmelar
IPC分类号： H04L25/03
CPC分类号： H04L27/01 , H04L25/03057 , H04L2025/03687 , H04L2025/037
摘要： Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.
摘要翻译：描述的实施例通过将一个或多个数据恢复比较器中的每一个的参考电压设置为相应的预定初始值来适配接收机的判决反馈均衡器的一个或多个抽头。数据恢复比较器为接收信号的每个采样产生一个位值。接收机的抽头适配模块选择n个接收位样本的窗口。对于一个或多个数据恢复比较器中的每一个，迭代地分接自适应模块，跟踪（i）具有逻辑0值的检测到的比特数，以及（ii）具有逻辑1值的检测到的比特数。抽头适配模块基于检测到的具有逻辑0值的位数与检测到的具有逻辑1值的位数的比率，将相应数据恢复比较器的参考电压调整预定步长量。

5. 发明申请

US20130243127A1 DYNAMIC DESKEW FOR BANG-BANG TIMING RECOVERY IN A COMMUNICATION SYSTEM 有权
标题翻译：用于通信系统中的BANG-BANG定时恢复的动态DESKEW
公开(公告)号：US20130243127A1
公开(公告)日：2013-09-19
申请号：US13422329
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H04L25/03057 , H04L2025/03363
摘要： Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled. The bang-bang trap iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin value and the voltage of the cursor bit, the margin phase detector determines whether the sample phase is correct.
摘要翻译：描述的实施例校准接收机的采样相位调整。模拟 - 数字转换器在采样阶段产生接收信号的采样。相位检测器选择n个样本的窗口。如果窗口包含奈奎斯特（Nyquist）模式，则会启用“爆炸”陷阱。迭代地，对于奈奎斯特图案中的第一连续位和第二连续位之间的每个转换，对第一和第二连续位之间的零交叉处的接收信号进行采样，并确定转换极性。基于过渡极性和零交叉采样值，轰击陷阱确定采样相位是否正确。如果窗口中不存在奈奎斯特图案，则边缘相位检测器确定窗口的目标电压余量值和光标位的电压。基于目标电压余量值和光标位电压，边缘相位检测器确定采样相位是否正确。

6. 发明申请

US20130243056A1 VOLTAGE MARGIN BASED BAUD RATE TIMING RECOVERY IN A COMMUNICATION SYSTEM 审中-公开
标题翻译：基于电压基准的波特率通信系统中的时钟恢复
公开(公告)号：US20130243056A1
公开(公告)日：2013-09-19
申请号：US13422226
申请日：2012-03-16
申请人： Erik V. Chmelar , Choshu Ito
发明人： Erik V. Chmelar , Choshu Ito
IPC分类号： H04B1/06 , H04B1/02 , H04B17/00
CPC分类号： H04L7/033
摘要： Described embodiments provide a method of recovering timing data from a received signal. An analog-to-digital converter (ADC) of a receiver generates an actual ADC value for each bit sample of a received signal. Each bit sample occurs at an associated sample phase of the receiver. A margin phase detector of the receiver recovers timing information from the received signal by determining a target voltage margin value. The margin phase detector selects a window of n received bit samples, where n is a positive integer, and determines a voltage of a cursor bit of the selected window of bit samples. The margin phase detector determines, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct. If the sample phase is incorrect, the margin phase detector adjusts the sample phase of the receiver by a predetermined amount.
摘要翻译：描述的实施例提供了一种从接收信号中恢复定时数据的方法。接收机的模数转换器（ADC）为接收信号的每个位采样产生实际的ADC值。每个位采样发生在接收器的相关采样相位。接收器的边沿相位检测器通过确定目标电压余量值来从接收信号中恢复定时信息。边缘相位检测器选择n个接收位样本的窗口，其中n是正整数，并且确定所选择的位采样窗口的光标位的电压。边缘相位检测器基于目标电压余量值和光标位的电压来确定采样相位是否正确。如果采样相位不正确，则边沿相位检测器将接收器的采样相位调整预定量。

7. 发明申请

US20100194616A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 有权
标题翻译：用于同步，重定时模数转换的系统和方法
公开(公告)号：US20100194616A1
公开(公告)日：2010-08-05
申请号：US12669481
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个，子级交错。在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和第四子电平交错同步到第一时钟相位。

8. 发明授权

US07696915B2 Analog-to-digital converter having reduced number of activated comparators 有权
标题翻译：具有减少的激活的比较器数量的模数转换器
公开(公告)号：US07696915B2
公开(公告)日：2010-04-13
申请号：US12108791
申请日：2008-04-24
申请人： Erik Chmelar , Choshu Ito
发明人： Erik Chmelar , Choshu Ito
IPC分类号： H03M1/36
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。

9. 发明申请

US20090296292A1 Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure 有权
标题翻译：采用微机电系统（MEMS）结构的静电放电保护电路
公开(公告)号：US20090296292A1
公开(公告)日：2009-12-03
申请号：US12128108
申请日：2008-05-28
申请人： Tze Wee Chen , William Loh , Choshu Ito
发明人： Tze Wee Chen , William Loh , Choshu Ito
IPC分类号： H02H9/00 , H01H59/00
CPC分类号： H01H59/0009 , H02H9/046
摘要： An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.
摘要翻译：用于保护耦合到信号垫的主机电路与在信号焊盘处发生的ESD事件的ESD保护电路包括至少一个电连接到信号焊盘的MEMS开关。 MEMS开关包括适于连接到信号焊盘的第一接触结构和适于连接到电压源的第二接触结构。在ESD事件期间，第一和第二接触结构耦合在一起，用于将ESD电流从信号焊盘分流到电压源。在没有ESD事件的情况下，第一和第二接触结构彼此电隔离。第一和第二接触结构中的至少一个包括用于减小第一和第二接触结构之间的接触粘附的钝化层。

10. 发明申请

US20090104735A1 SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE 有权
标题翻译：具有抗静电放电电阻的半导体封装
公开(公告)号：US20090104735A1
公开(公告)日：2009-04-23
申请号：US12337519
申请日：2008-12-17
申请人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
发明人： Choshu Ito , William M. Loh , Rajagopalan Parthasarathy
IPC分类号： H01L21/50
CPC分类号： H01L23/60 , H01L23/552 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16251 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。该封装包括附接到基板的ESD屏蔽。 ESD屏蔽被配置为增加封装的ESD硬度。 ESD屏蔽件可进一步用于加强封装以防止翘曲并作为散热器进行操作。

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