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1. 发明授权

US06383874B1 In-situ stack for high volume production of isolation regions 有权
标题翻译：原位堆叠用于大批量生产隔离区
公开(公告)号：US06383874B1
公开(公告)日：2002-05-07
申请号：US09800862
申请日：2001-03-07
申请人： Sey-Ping Sun , Mark I. Gardner , Robert W. Anderson
发明人： Sey-Ping Sun , Mark I. Gardner , Robert W. Anderson
IPC分类号： H01L21336
CPC分类号： H01L21/76224
摘要： A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing interface. An oxide film is formed on the nitrogen containing interface and a silicon rich nitride film is formed on the oxide film. The silicon rich nitride film is exposed to a plasma ambient containing oxygen to convert an upper portion of the silicon rich nitride film to silicon oxynitride. The optical properties of the nitride film are enhanced so that UV lithographic patterning of etch masking is improved.
摘要翻译：提供了用于制造隔离结构的器件堆叠及其制造方法。在一个方面，提供了一种处理衬底的方法，其包括将衬底暴露于含有氮和氧的等离子体环境中以形成含氮界面。在含氮界面上形成氧化膜，在氧化物膜上形成富含氮的氮化物膜。富硅氮化物膜暴露于含有氧的等离子体环境，以将富硅氮化物膜的上部转化为氮氧化硅。氮化膜的光学特性得到增强，从而提高了蚀刻掩模的UV光刻图案。

2. 发明授权

US06258730B1 Ultra-thin gate oxide formation using an N2O plasma 有权
标题翻译：使用N2O等离子体的超薄栅极氧化物形成
公开(公告)号：US06258730B1
公开(公告)日：2001-07-10
申请号：US09246462
申请日：1999-02-09
申请人： Sey-Ping Sun , Mark I. Gardner , Shengnian Song
发明人： Sey-Ping Sun , Mark I. Gardner , Shengnian Song
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/31662
摘要： A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N2O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N2O plasma is created by applying RF power to a showerhead from which the N2O is dispensed. By reacting an N2O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N2O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N2O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N2O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation. Following gate oxide formation, a high temperature anneal may be performed, preferably in an RTA apparatus. By combining the N2O plasma treatment with an RTA process, the disclosed method is believed to offer a controllable and reproducible method for fabricating highly uniform, ultra-thin gate oxides, having low trapping state densities.
摘要翻译：公开了用于形成超薄栅极氧化物的半导体器件的制造工艺，由此使硅衬底经受N 2 O等离子体以形成超薄栅极氧化物。根据一个实施例，在沉积室中加热硅衬底，并且通过将RF功率施加到分配N2O的喷头来产生N 2 O等离子体。通过使N2O等离子体直接与硅衬底反应，可以实现厚度小于20的栅极氧化物和小于1％标准偏差的相对均匀性。由本发明的N2O等离子体处理产生的氧化物生长速度比其它已知的氧化物形成技术慢得多。所公开的N2O等离子体处理对热氧化的一个优点在于与N2O等离子体反应产生的氧化物生长厚度与热氧化显示的氧化物形成速率的强烈变化的可预测性。在形成栅极氧化物之后，可以优选在RTA装置中进行高温退火。通过将N2O等离子体处理与RTA工艺结合，所公开的方法被认为是提供具有低陷阱状态密度的制造高度均匀的超薄栅极氧化物的可控和可再现的方法。

3. 发明授权

US6051876A Semiconductor device with a graded passivation layer 失效
标题翻译：具有渐变钝化层的半导体器件
公开(公告)号：US6051876A
公开(公告)日：2000-04-18
申请号：US2651
申请日：1998-01-05
申请人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
发明人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
IPC分类号： H01L23/31 , H01L23/48
CPC分类号： H01L23/3171 , H01L2924/0002 , H01L2924/13091
摘要： The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.
摘要翻译：公开了渐变钝化层的形成。在一个实施例中，一种方法包括四个步骤。在第一步骤中，提供半导体衬底上的至少一个晶体管。在第二步骤中，在至少一个晶体管上形成至少一个金属化层。在第三步骤中，氧化物层沉积在至少一个金属化层上。最后，在第四步骤中，施加预定掺杂剂的离子注入以在至少一个金属化层上产生渐变钝化膜。

4. 发明授权

US06259133B1 Method for forming an integrated circuit memory cell and product thereof 有权
标题翻译：用于形成集成电路存储单元的方法及其制造方法
公开(公告)号：US06259133B1
公开(公告)日：2001-07-10
申请号：US09248432
申请日：1999-02-11
申请人： Mark I. Gardner , Sey-Ping Sun
发明人： Mark I. Gardner , Sey-Ping Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/0688 , H01L27/115 , H01L27/11541 , H01L27/11551 , H01L29/42324 , H01L29/7883
摘要： A method for fabricating an integrated circuit is presented. In the method, a dielectric layer is formed, and then a conductive layer is formed upon the dielectric layer. A base gate may then be patterned from the conductive layer. An intergate dielectric is preferably formed over and around the base gate. A spacer gate may then be formed such that at least a portion of the spacer gate is elevationally below an upper portion of the base gate. At least a portion of the intergate dielectric layer is preferably interposed between a sidewall surface of the spacer gate and a sidewall surface of the base gate. The final memory cell fabricated in this manner does not need to transfer electrons from a semiconducting substrate during operation.
摘要翻译：提出了一种用于制造集成电路的方法。在该方法中，形成介电层，然后在电介质层上形成导电层。然后可以从导电层图案化基栅。优选地，在基栅上方和周围形成隔间电介质。然后可以形成间隔栅，使得间隔栅的至少一部分在基栅的上部的正上方。隔间电介质层的至少一部分优选插入在间隔栅极的侧壁表面和基栅的侧壁表面之间。以这种方式制造的最终存储单元在操作期间不需要从半导体衬底传输电子。

5. 发明授权

US6150286A Method of making an ultra thin silicon nitride film 有权
标题翻译：制造超薄氮化硅膜的方法
公开(公告)号：US6150286A
公开(公告)日：2000-11-21
申请号：US477050
申请日：2000-01-03
申请人： Sey-Ping Sun , Mark I. Gardner , Shengnian Song
发明人： Sey-Ping Sun , Mark I. Gardner , Shengnian Song
IPC分类号： H01L21/28 , H01L21/318 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/518 , H01L21/3185 , Y10S438/958
摘要： Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.
摘要翻译：提供了使用氮化硅制造电路结构的各种方法。一方面，提供一种制造电路结构的方法，其包括在硅表面上形成氮化硅膜，在氮气环境中退火氮化硅膜，并在氮氧化物环境中退火氮化硅膜以形成薄氧化物在氮化硅膜和硅表面之间的界面处。本发明的方法能够制造具有高度均匀形态的薄氮化硅膜用作栅极电介质或其它目的。薄氧化膜的厚度是自限制的，并且改善了不同的机械应力。

6. 发明授权

US6124217A In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的用于减少层间电介质缺陷的原位SiON沉积/烘烤/ TEOS沉积工艺
公开(公告)号：US6124217A
公开(公告)日：2000-09-26
申请号：US200016
申请日：1998-11-25
申请人： Sey-Ping Sun , Mark I. Gardner , Minh Van Ngo
发明人： Sey-Ping Sun , Mark I. Gardner , Minh Van Ngo
IPC分类号： C23C16/30 , C23C16/56 , H01L21/314 , H01L21/318 , H01L21/768 , H01L23/522 , H01L29/78 , H01L21/31
CPC分类号： H01L21/76801 , H01L21/3145 , H01L21/76828 , H01L21/76834
摘要： An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use in integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.
摘要翻译：形成包含原硅酸四乙酯（TEOS）氧化物和氧氮化硅（SiON）蚀刻停止层的层间电介质用于集成电路制造。 SiON层沉积在可包括晶体管和/或互连级别的半导体衬底上。在沉积TEOS层之前加热SiON层。 SiON层的加热大大减少了在TEOS沉积期间形成的缺陷的数量。由此形成高度保形的高品质层间电介质。

7. 发明授权

US06251800B1 Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance 失效
标题翻译：使用低功率，低压PECVD的超薄沉积栅介质形成，以改善半导体器件性能
公开(公告)号：US06251800B1
公开(公告)日：2001-06-26
申请号：US09227513
申请日：1999-01-06
申请人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
发明人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/28194 , H01L21/31612
摘要： An ultrathin gate dielectric and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) method employing silane and nitrous oxide sources is used to deposit the dielectric. As compared to conventional PECVD deposition, the method uses lower silane and nitrous oxide flow rates, a more dilute silane in nitrogen mixture, a lower chamber pressure, and a lower radio frequency power density. These settings allow plasma conditions to stabilize so that deposition may be performed in time increments at least as short as 0.1 second, so that oxide thicknesses at least as small as one angstrom may be controllably deposited. The oxide is preferably deposited in portions at multiple substrate mounting positions in a deposition chamber. Combination of oxide portions in this manner is believed to reduce the density of pinholes in the oxide, and the low-power, low-pressure deposition conditions are further believed to reduce plasma damage to the oxide and reduce the density of trap states in the oxide. A rapid thermal anneal of the oxide may be performed after deposition, and may improve the quality of the interface between the oxide and the underlying semiconductor substrate.
摘要翻译：提供一种超薄栅极电介质及其形成方法。认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。使用采用硅烷和一氧化二氮源的低功率，低压等离子体增强化学气相沉积（PECVD）方法沉积电介质。与传统的PECVD沉积相比，该方法使用较低的硅烷和一氧化二氮流率，氮混合物中更稀的硅烷，较低的室压力和较低的射频功率密度。这些设置允许等离子体条件稳定，使得可以以至少短至0.1秒的时间增量执行沉积，使得至少小至一埃的氧化物厚度可以可控地沉积。优选在沉积室中的多个基板安装位置处部分地沉积氧化物。认为以这种方式组合氧化物部分可以降低氧化物中针孔的密度，并且进一步认为低功率，低压沉积条件可减少对氧化物的等离子体损伤并降低氧化物中陷阱态的密度。可以在沉积之后进行氧化物的快速热退火，并且可以提高氧化物和下面的半导体衬底之间的界面的质量。

8. 发明授权

US6140688A Semiconductor device with self-aligned metal-containing gate 有权
标题翻译：具有自对准含金属栅极的半导体器件
公开(公告)号：US6140688A
公开(公告)日：2000-10-31
申请号：US157627
申请日：1998-09-21
申请人： Mark I. Gardner , Sey-Ping Sun
发明人： Mark I. Gardner , Sey-Ping Sun
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L29/76
CPC分类号： H01L27/105 , H01L21/28061 , H01L21/28273 , H01L21/82345 , H01L27/088 , H01L27/11526 , H01L27/11531 , H01L27/11543 , H01L29/6659 , H01L29/66825 , H01L27/11529 , H01L29/66545
摘要： A semiconductor device is provided and formed using self-aligned metal-containing gates within a metal-oxide semiconductor (MOS) process. After forming junction regions within a semiconductor substrate, the gate conductor, or junction implant alignment structure, is at least partially removed to form a trench within a dielectric formed above the substrate. Upper surfaces of the transistor, except the upper surface of the gate conductor, are thereby protected by the dielectric. A metal-containing material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The metal material can be formed either as a single layer or as multiple metal and/or dielectric layers interposed throughout the as-filled trench. The metal-filled trench formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的含金属栅极提供并形成半导体器件。在半导体衬底中形成接合区域之后，至少部分去除栅极导体或结植入对准结构，以在衬底上形成的电介质内形成沟槽。除了栅极导体的上表面之外，晶体管的上表面被电介质保护。然后可以在沟槽内，即在去除栅极导体的区域中布置含金属的材料。金属材料可以形成为单层或多个金属和/或介电层插入整个填充的沟槽中。金属填充的沟槽形成在高温循环之后发生，通常与激活先前注入的结或生长栅极电介质相关联。因此，可以使用诸如铜或铜合金的低温金属。

9. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

10. 发明授权

US06979878B1 Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites 失效
标题翻译：隔离结构在隔离槽的顶角处注入硅原子填充空位和间隙位置
公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

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