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1. 发明授权

US08225315B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US08225315B1
公开(公告)日：2012-07-17
申请号：US11933319
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
IPC分类号： G06F9/455 , G06F15/76
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
摘要翻译：一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。第一个虚拟内核映射到物理内核。虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到响应虚拟核心管理组件检测物理内核空闲的物理核心。

2. 发明授权

US07802073B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US07802073B1
公开(公告)日：2010-09-21
申请号：US11781726
申请日：2007-07-23
申请人： Yu Qing Cheng , John Gregory Favor , Carlos Puchol , Seungyoon Peter Song , Peter Glaskowsky , Laurent Moll , Joe Rowlands , Donald Alpert
发明人： Yu Qing Cheng , John Gregory Favor , Carlos Puchol , Seungyoon Peter Song , Peter Glaskowsky , Laurent Moll , Joe Rowlands , Donald Alpert
IPC分类号： G06F9/50
CPC分类号： G06F9/3851
摘要： The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.
摘要翻译：本公开提供适于与具有一个或多个物理核心的处理器一起使用的方法和系统。所述方法和系统包括适于将一个或多个虚拟核心映射到所述物理核心中的至少一个的虚拟核心管理组件，以使所述至少一个物理核心能够执行一个或多个程序。一个或多个虚拟核心包括与一个或多个程序的执行相关联的一个或多个逻辑状态。方法和系统可以包括适于存储一个或多个虚拟核的存储器组件。虚拟核心管理组件可以适于将一个或多个虚拟核心从存储器组件传送到至少一个物理核心。

3. 发明授权

US07797512B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US07797512B1
公开(公告)日：2010-09-14
申请号：US11933297
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/46
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.
摘要翻译：包括一个或多个物理核心和一个或多个虚拟核心的虚拟核心管理系统。每个虚拟核心分别包括与相应程序的执行相关联的逻辑状态的集合。虚拟核心管理系统还包括一个或多个中断控制器，其被配置为发送一个或多个中断信号以中断与一个或多个虚拟核心中的至少一个虚拟核心相关联的对应程序的执行;以及虚拟核心管理组件，至少一个虚拟内核到一个或多个物理核心中的一个，并将一个或多个中断信号路由到相应的物理核心。

4. 发明授权

US07673122B1 Software hint to specify the preferred branch prediction to use for a branch instruction 有权
标题翻译：软件提示指定用于分支指令的首选分支预测
公开(公告)号：US07673122B1
公开(公告)日：2010-03-02
申请号：US11306000
申请日：2005-12-16
申请人： Seungyoon Peter Song , John Gregory Favor , Richard W. Thaik
发明人： Seungyoon Peter Song , John Gregory Favor , Richard W. Thaik
IPC分类号： G06F9/00
CPC分类号： G06F9/3846 , G06F9/3848
摘要： Software hints embedded in branch instructions direct selection of one of a plurality of branch predictors to use when processing the branch instructions, leading to improved branch prediction (i.e. fewer mis-predictions) over conventional schemes. A software agent assembles branch instructions having associated respective branch predictor control fields compatible with a branch predictor selector and a plurality of branch predictors. Each branch predictor control field is used to perform branch predictor selection, branch predictor control, or both. Branch predictor selection enables selective branch prediction according to an appropriate one of the branch predictors as determined by the software agent by examining context surrounding the branch instruction. Branch predictor control enables control of operation of one or more of the branch predictors. For example, a history-based branch predictor may be instructed to provide branch prediction according to a history-depth specified by the branch predictor control.
摘要翻译：嵌入分支指令中的软件提示直接选择在处理分支指令时使用的多个分支预测器中的一个，导致与常规方案相比改进的分支预测（即较少的误预测）。软件代理装配具有与分支预测器选择器和多个分支预测器兼容的相关联的相应分支预测器控制字段的分支指令。每个分支预测器控制字段用于执行分支预测器选择，分支预测器控制或两者。分支预测器选择通过检查分支指令周围的上下文，根据由软件代理确定的适当的一个分支预测器启用选择性分支预测。分支预测器控制使得能够控制一个或多个分支预测器的操作。例如，可以指示基于历史的分支预测器，以根据由分支预测器控制指定的历史深度来提供分支预测。

5. 发明授权

US07587585B1 Flag management in processors enabled for speculative execution of micro-operation traces 有权
标题翻译：处理器中的标志管理能够推测微操作轨迹的执行
公开(公告)号：US07587585B1
公开(公告)日：2009-09-08
申请号：US11553453
申请日：2006-10-26
申请人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
发明人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30094 , G06F9/3808 , G06F9/3863
摘要： Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags during atomic trace renaming in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is stored when an atomic trace is renamed. An action that updates flags updates all entries in the table corresponding to younger atomic traces. If the atomic trace is aborted, then the corresponding flag checkpoint is used for restoration of flag state.
摘要翻译：通过与原子轨迹对应的一个或多个动作的组来管理推测性执行，可以有效地处理与标志相关的动作，因为原子轨迹有利地使原子轨迹边界上的标志值的检查点成为可能。在处理器系统中的原子轨迹重命名期间的检查点标志使用标志检查点表来存储多个标志检查点，每个对应于原子轨迹。当原子轨迹中止时，有选择地访问该表以提供标志信息来恢复推测标志。当重新命名原子轨迹时，存储对应的标志检查点。更新标志的操作会更新表中对应于较年轻原子轨迹的所有条目。如果原子轨迹中止，则对应的标志检查点用于恢复标志状态。

6. 发明授权

US07533242B1 Prefetch hardware efficiency via prefetch hint instructions 有权
标题翻译：通过预取提示指令预取硬件效率
公开(公告)号：US07533242B1
公开(公告)日：2009-05-12
申请号：US11279880
申请日：2006-04-15
申请人： Laurent R. Moll , Jorel D. Hartman , Peter N. Glaskowsky , Seungyoon Peter Song , John Gregory Favor
发明人： Laurent R. Moll , Jorel D. Hartman , Peter N. Glaskowsky , Seungyoon Peter Song , John Gregory Favor
IPC分类号： G06F9/26
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F2212/1021 , G06F2212/6028
摘要： A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to execute instructions according to the instruction set architecture. The prefetch hints are directed to control operation of one or more hardware memory prefetcher units included in the processor, providing for increased efficiency in memory prefetching operations. The hints may optionally provide any combination of parameters describing a memory reference traffic pattern to search for, when to begin searching, when to terminate prefetching, and how aggressively to prefetch. Thus the hardware prefetchers are enabled to make improved traffic prediction, providing more accurate results using reduced hardware resources. The hints may include any combination of specific pattern hints (one/two/N-dimensional strides, indirect, and indirect-stride), modifiers including sparse and region, and a prefetch-stop directive. The parameters may include any combination of a count, a priority and a ramp.
摘要翻译：软件代理装配在指令集架构中定义的预取提示指令或前缀，指令/前缀将预取提示信息传送到能够根据指令集架构执行指令的处理器。预取提示旨在控制包括在处理器中的一个或多个硬件存储器预取器单元的操作，从而提高存储器预取操作的效率。提示可以可选地提供描述存储器参考流量模式的参数的任何组合以搜索，何时开始搜索，何时终止预取，以及如何积极地预取。因此，硬件预取器能够进行改进的流量预测，使用减少的硬件资源提供更准确的结果。提示可以包括特定模式提示（一/二/ N维步幅，间接和间接步幅），包括稀疏和区域的修饰符以及预取停止指令的任何组合。这些参数可以包括计数，优先级和斜坡的任何组合。

7. 发明授权

US5644779A Processing system and method of operation for concurrent processing of branch instructions with cancelling of processing of a branch instruction 失效
标题翻译：处理系统和分支指令并行处理方法，取消分支指令的处理
公开(公告)号：US5644779A
公开(公告)日：1997-07-01
申请号：US228249
申请日：1994-04-15
申请人： Seungyoon Peter Song
发明人： Seungyoon Peter Song
IPC分类号： G06F9/38
CPC分类号： G06F9/30061 , G06F9/3842 , G06F9/3863 , G06F9/3885
摘要： A processing system and method of operation are provided. In response to multiple branch instructions, an instruction is processed prior to execution of the branch instructions. In response to execution of any of the branch instructions, the processing of the instruction is cancelled prior to completion of the executed branch instruction.
摘要翻译：提供了一种处理系统和操作方法。响应于多个分支指令，在执行分支指令之前处理指令。响应于任何分支指令的执行，指令的处理在执行的分支指令完成之前被取消。

8. 发明授权

US07631207B1 Reducing power consumption for processing of common values in microprocessor registers and execution units 有权
标题翻译：降低处理微处理器寄存器和执行单元中常用值的功耗
公开(公告)号：US07631207B1
公开(公告)日：2009-12-08
申请号：US11408784
申请日：2006-04-21
申请人： Seungyoon Peter Song , Jorel Hartman
发明人： Seungyoon Peter Song , Jorel Hartman
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/30156 , G06F9/3016 , G06F9/3017 , G06F9/383
摘要： Reducing power consumption in microprocessors for the processing of common values. Common values provided in at least one received operation are encoded into encoded common values having a lower number of bits than the common values prior to encoding. In one aspect, a separate encoding bus is used to provide the encoded common values in various processing of additional received operations in the microprocessor instead of a full-bit bus of the microprocessor, the encoding bus having less bits than the full-bit bus. In another aspect, a result of the operation is predicted based on at least one encoded common value and execution of the operation is bypassed.
摘要翻译：微处理器的功耗降低，用于处理普通值。在至少一个接收到的操作中提供的公共值被编码成具有比编码之前的公共值低的位数的编码公共值。在一个方面，单独的编码总线用于在微处理器中的附加接收操作的各种处理中提供编码的公共值，而不是微处理器的全位总线，编码总线具有比全位总线更少的位。在另一方面，基于至少一个编码的公共值来预测操作的结果，并且绕过该操作的执行。

9. 发明授权

US07568088B1 Flag management in processors enabled for speculative execution of micro-operation traces 有权
标题翻译：处理器中的标志管理能够推测微操作轨迹的执行
公开(公告)号：US07568088B1
公开(公告)日：2009-07-28
申请号：US11553455
申请日：2006-10-26
申请人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
发明人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30094 , G06F9/3808 , G06F9/3863
摘要： Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags on-demand for atomic traces in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is allocated to an invalid state when an atomic trace is renamed. An action that updates flags initializes the corresponding flag checkpoint (if invalid). If the atomic trace is aborted, then the table is searched according to program order starting with the entry corresponding to the aborted atomic trace. The first (if any) valid checkpoint found is used for flag restoration.
摘要翻译：通过与原子轨迹对应的一个或多个动作的组来管理推测性执行，可以有效地处理与标志相关的动作，因为原子轨迹有利地使原子轨迹边界上的标志值的检查点成为可能。处理器系统中原子轨迹的点对点标志使用标志检查点表来存储多个对应于原子轨迹的标志检查点。当原子轨迹中止时，有选择地访问该表以提供标志信息来恢复推测标志。当重命名原子轨迹时，相应的标志检查点被分配到无效状态。更新标志的动作初始化相应的标志检查点（如果无效）。如果原子轨迹被中止，那么根据程序顺序搜索表格，从与中止的原子轨迹对应的条目开始。找到的第一个（如果有的话）有效检查点用于标志恢复。

10. 发明授权

US07412570B2 Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state 有权
标题翻译：小而高功率的缓存，可在处理器处于低功耗状态时为背景DNA设备提供数据
公开(公告)号：US07412570B2
公开(公告)日：2008-08-12
申请号：US11351058
申请日：2006-02-09
申请人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
发明人： Laurent R. Moll , Yu Qing Cheng , Peter N. Glaskowsky , Seungyoon Peter Song
IPC分类号： G06F13/14
CPC分类号： G06F12/0835 , G06F12/0875 , G06F13/28 , G06F2212/1028 , Y02D10/13
摘要： A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
摘要翻译：当微处理器中的高速缓存数据由于微处理器中的任何一个或全部处于低电平状态而无法访问时，小型和功率高效的缓冲器/微型缓存器将选择的DMA访问定向到微处理器的相干域中的存储器空间电源状态不支持窥探。通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存数据同步。或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。

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