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1. 发明授权

US07802073B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US07802073B1
公开(公告)日：2010-09-21
申请号：US11781726
申请日：2007-07-23
申请人： Yu Qing Cheng , John Gregory Favor , Carlos Puchol , Seungyoon Peter Song , Peter Glaskowsky , Laurent Moll , Joe Rowlands , Donald Alpert
发明人： Yu Qing Cheng , John Gregory Favor , Carlos Puchol , Seungyoon Peter Song , Peter Glaskowsky , Laurent Moll , Joe Rowlands , Donald Alpert
IPC分类号： G06F9/50
CPC分类号： G06F9/3851
摘要： The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.
摘要翻译：本公开提供适于与具有一个或多个物理核心的处理器一起使用的方法和系统。所述方法和系统包括适于将一个或多个虚拟核心映射到所述物理核心中的至少一个的虚拟核心管理组件，以使所述至少一个物理核心能够执行一个或多个程序。一个或多个虚拟核心包括与一个或多个程序的执行相关联的一个或多个逻辑状态。方法和系统可以包括适于存储一个或多个虚拟核的存储器组件。虚拟核心管理组件可以适于将一个或多个虚拟核心从存储器组件传送到至少一个物理核心。

2. 发明授权

US06584558B2 Article for providing event handling functionality in a processor supporting different instruction sets 有权
标题翻译：用于在支持不同指令集的处理器中提供事件处理功能的文章
公开(公告)号：US06584558B2
公开(公告)日：2003-06-24
申请号：US10132554
申请日：2002-04-24
申请人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
发明人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
IPC分类号： G06F940
CPC分类号： G06F9/4812 , G06F9/30181 , G06F9/3822
摘要： An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.
摘要翻译：描述了表示提供事件处理功能的处理器的文章。根据本发明的一个实施例，该物品包括存储表示包括指令集单元和事件处理单元的处理器的数据的机器可读介质，以及包括第一事件处理程序的第一多个事件处理程序。指令集单元支持第一和第二指令集。在处理来自第一和第二单元的指令期间出现的问题是使物品执行第一多个事件处理程序中适当的一个。第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。所有第二组事件都映射到第一个事件处理程序。

3. 发明授权

US06219774B1 Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture 失效
标题翻译：地址转换/旁路中间分段转换以适应两种不同的指令集架构
公开(公告)号：US06219774B1
公开(公告)日：2001-04-17
申请号：US09048241
申请日：1998-03-25
申请人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
发明人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
IPC分类号： G06F1210
CPC分类号： G06F9/4812 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F9/3822
摘要： A Method and Apparatus for Providing Memory Management and Event Handling Functionality in a Computer System. According to one embodiment of the invention, a processor comprises an instruction set unit, a segmentation unit, and a paging unit. The instruction set unit is to support a first and second instruction sets. The segmentation unit is coupled to the instruction set unit to translate virtual addresses used by the first instruction set into translated addresses. The paging unit is coupled to the instruction set unit to translate both virtual addresses used by the second instruction set and the translated addresses into physical addresses. According to another embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second instruction sets respectively causes a first and second set of events. The event handling unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.
摘要翻译：一种用于在计算机系统中提供存储器管理和事件处理功能的方法和装置。根据本发明的一个实施例，处理器包括指令集单元，分割单元和寻呼单元。指令集单元支持第一和第二指令集。分割单元耦合到指令集单元以将由第一指令集使用的虚拟地址转换为转换的地址。寻呼单元耦合到指令集单元以将由第二指令集使用的两个虚拟地址和转换的地址转换成物理地址。根据本发明的另一实施例，计算机系统包括处理器中的指令集单元和事件处理单元，以及包括第一事件处理程序的第一多个事件处理程序。指令集单元支持第一和第二指令集。在处理来自第一和第二指令集的指令期间出现的问题分别导致第一和第二组事件。事件处理单元是使处理器执行第一组多个事件处理程序中适当的一个。第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。所有第二组事件都映射到第一个事件处理程序。

4. 发明授权

US5991874A Conditional move using a compare instruction generating a condition field 失效
标题翻译：使用生成条件字段的比较指令进行条件移动
公开(公告)号：US5991874A
公开(公告)日：1999-11-23
申请号：US660094
申请日：1996-06-06
申请人： Jack D. Mills , Donald Alpert
发明人： Jack D. Mills , Donald Alpert
IPC分类号： G06F9/30 , G06F9/315 , G06F9/38 , G06F7/00 , G06F7/38
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/30072 , G06F9/384
摘要： An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element B. In response to a single instruction, the circuit performs the comparison and outputs a condition field of at least one bits when the comparison of A and B is TRUE, or else the circuit outputs the ones-complement of the condition field when the comparison of A and B is FALSE. The circuit may be used in conjunction with a sequence of instructions to select bits from a first data element and bits from a second data element using the one or more condition field bits.
摘要翻译：一种在计算机系统中使用的装置包括耦合到第一存储区域的第一存储区域和电路，被配置为执行数据元素A与数据元素B的比较。响应于单个指令，电路执行当A和B的比较为TRUE时，比较并输出至少一个比特的条件字段，否则当A和B的比较为FALSE时，电路输出条件字段的补码。电路可以与指令序列一起使用，以使用一个或多个条件字段位来从第一数据元素选择位和来自第二数据元素的位。

5. 发明授权

US5774686A Method and apparatus for providing two system architectures in a processor 失效
标题翻译：用于在处理器中提供两个系统架构的方法和装置
公开(公告)号：US5774686A
公开(公告)日：1998-06-30
申请号：US482239
申请日：1995-06-07
申请人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
发明人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
IPC分类号： G06F9/318 , G06F9/38 , G06F9/48 , G06F9/30
CPC分类号： G06F9/4812 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F9/3822
摘要： A processor having two system configurations is provided. The apparatus generally includes an instruction set unit, a system unit, an internal bus, and a bus unit. The instruction set unit, the system unit, and the bus unit are coupled together by the internal bus. The system unit is capable of selectively operating in one of two system configurations. The first system configuration provides a first system architecture, while the second system configuration provides a second system architecture. The bus unit is used for sending and receiving signals from the instruction set unit and the system unit. According to another aspect of the invention, the instruction set unit is capable of selectively operating in one of two instruction set configurations. The first instruction set configuration provides for the execution of instruction belonging to a first instruction set, while the second instruction set configuration provides for the execution of instructions belonging to a second instruction set.
摘要翻译：提供具有两个系统配置的处理器。该装置通常包括指令集单元，系统单元，内部总线和总线单元。指令集单元，系统单元和总线单元通过内部总线耦合在一起。系统单元能够选择性地在两种系统配置之一中操作。第一系统配置提供第一系统架构，而第二系统配置提供第二系统架构。总线单元用于从指令集单元和系统单元发送和接收信号。根据本发明的另一方面，指令集单元能够选择性地以两种指令集配置中的一种进行操作。第一指令集配置提供执行属于第一指令集的指令，而第二指令集配置提供属于第二指令集的指令的执行。

6. 发明授权

US5659679A Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system 失效
标题翻译：在计算机系统中提供断点和提供软件分析的方法和装置
公开(公告)号：US5659679A
公开(公告)日：1997-08-19
申请号：US454087
申请日：1995-05-30
申请人： Donald Alpert , Gary N. Hammond
发明人： Donald Alpert , Gary N. Hammond
IPC分类号： G06F11/36 , G06F11/34
CPC分类号： G06F11/3648 , G06F11/3636
摘要： According to one aspect of the invention, an apparatus for providing the source address of an instruction which causes a branch to be taken (e.g., instructs the processor to transfer the flow of execution) is described. In one embodiment, a processor includes a circuit coupled to a source address storage area. In response to the processor executing an instruction which instructs the processor to transfer the flow of execution to another instruction, the circuit stores in the source address storage area the address of the instruction which is causing the transfer in flow of execution.According to another aspect of the invention, a method for profiling is provided. According to this method, a starting address for execution is stored. Then for the instruction currently being executed, it is determined if that instruction will cause a branch from a source address to a destination address. If it was determined a branch will be taken, then the source address of the branch is stored in a source address storage area, the destination address of the branch is stored in another storage area, and a handler is executed. The handler stores indications indicating the instructions identified by the addresses within the address range defined by the starting address and the source address have been executed.
摘要翻译：根据本发明的一个方面，描述了一种用于提供引起分支的指令的源地址（例如，指示处理器传送执行流程）的装置。在一个实施例中，处理器包括耦合到源地址存储区域的电路。响应于处理器执行指示处理器将执行流程传送到另一指令的指令，电路在源地址存储区域中存储正在导致执行流程的指令的地址。根据本发明的另一方面，提供了一种用于轮廓的方法。根据该方法，存储执行的起始地址。然后，对于当前正在执行的指令，确定该指令是否会导致从源地址到目标地址的分支。如果确定将分支，则将分支的源地址存储在源地址存储区域中，将分支的目的地址存储在另一个存储区域中，并执行处理程序。处理器存储指示由起始地址和源地址定义的地址范围内的地址所标识的指令已被执行的指示。

7. 发明授权

US06408386B1 Method and apparatus for providing event handling functionality in a computer system 有权
标题翻译：用于在计算机系统中提供事件处理功能的方法和装置
公开(公告)号：US06408386B1
公开(公告)日：2002-06-18
申请号：US09770970
申请日：2001-01-25
申请人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
发明人： Gary Hammond , Donald Alpert , Kevin Kahn , Harsh Sharangpani
IPC分类号： G06F940
CPC分类号： G06F9/4812 , G06F9/30181 , G06F9/3822
摘要： Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.
摘要翻译：在计算机系统中提供事件处理功能的方法和装置。根据本发明的一个实施例，计算机系统包括处理器中的指令集单元和事件处理单元，以及包括第一事件处理程序的第一多个事件处理程序。指令集单元支持第一和第二指令集。在处理来自第一和第二单元的指令期间出现的问题是使处理器执行第一组多个事件处理程序中适当的一个。第一组事件中的至少一些映射到第一组多个事件处理程序中的不同的事件。所有第二组事件都映射到第一个事件处理程序。

8. 发明授权

US06052801A Method and apparatus for providing breakpoints on a selectable address range 失效
标题翻译：用于在可选地址范围上提供断点的方法和装置
公开(公告)号：US06052801A
公开(公告)日：2000-04-18
申请号：US438474
申请日：1995-05-10
申请人： Gary N. Hammond , Donald Alpert
发明人： Gary N. Hammond , Donald Alpert
IPC分类号： G06F11/36 , G06F11/30 , G06F12/00
CPC分类号： G06F11/3648
摘要： A method and apparatus for providing breakpoints on a selectable address range. The apparatus generally includes a processor including a first storage area, a second storage area, a circuit and an execution unit. The first storage area has stored therein a first address, while the second storage area has stored therein a mask. The first address and the mask define an address range. In response to receiving a second address, the circuit accesses the first address stored in the first storage area and the mask stored in the second storage area. The circuit transmits a signal to cause a debug event if the second address is within the address range defined by the first address and the mask.
摘要翻译：一种用于在可选地址范围上提供断点的方法和装置。该装置通常包括处理器，该处理器包括第一存储区域，第二存储区域，电路和执行单元。第一存储区域已经存储有第一地址，而第二存储区域已经存储有掩模。第一个地址和掩码定义一个地址范围。响应于接收到第二地址，电路访问存储在第一存储区域中的第一地址和存储在第二存储区域中的掩码。如果第二地址在由第一地址和掩码定义的地址范围内，则电路发送信号以引起调试事件。

9. 发明授权

US5729724A Adaptive 128-bit floating point load and store operations for quadruple precision compatibility 失效
标题翻译：自适应128位浮点加载和存储操作，用于四重精度兼容性
公开(公告)号：US5729724A
公开(公告)日：1998-03-17
申请号：US580035
申请日：1995-12-20
申请人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
发明人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
IPC分类号： G06F5/00 , G06F9/302 , G06F9/312 , G06F7/00
CPC分类号： G06F9/30014 , G06F5/00 , G06F9/30036 , G06F9/30043
摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.
摘要翻译：一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。剩余的位位置用0填充。当值移动到存储器时，执行相反的操作。

10. 发明申请

US20050091480A1 Computer system and method for executing interrupt instructions in operating modes 审中-公开
标题翻译：用于在操作模式下执行中断指令的计算机系统和方法
公开(公告)号：US20050091480A1
公开(公告)日：2005-04-28
申请号：US10982217
申请日：2004-11-05
申请人： John Crawford , Donald Alpert
发明人： John Crawford , Donald Alpert
IPC分类号： G06F9/318 , G06F9/455 , G06F9/46 , G06F9/48 , G06F7/38 , G06F9/00
CPC分类号： G06F9/4812 , G06F9/45533
摘要： A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.
摘要翻译：本文公开了一种计算机系统，其包括专门设计为在虚拟操作模式下操作的给定微处理器，其允许先前为先前设计的单个程序微处理器写入的软件程序在受特定设计的主机之下的受保护的，分页的多任务环境中执行操作软件程序。该系统还包括使用形成主机程序的一部分的仿真软件来执行软件中断（INTn）指令的装置，以便模拟这些指令将由较早的微处理器执行的方式。作为对整个计算机系统的独特改进，INTn指令中的某些指令通过仿真软件执行，而其他指令则通过与给定的微处理器及其主机操作软件程序协作的先前编写的程序来执行。

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