专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08462558B2 Program and erase methods for nonvolatile memory 有权
标题翻译：非易失性存储器的编程和擦除方法
公开(公告)号：US08462558B2
公开(公告)日：2013-06-11
申请号：US12805500
申请日：2010-08-03
申请人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
发明人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3404
摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.
摘要翻译：编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲，软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。

2. 发明申请

US20100302861A1 Program and erase methods for nonvolatile memory 有权
公开(公告)号：US20100302861A1
公开(公告)日：2010-12-02
申请号：US12805500
申请日：2010-08-03
申请人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
发明人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/3404
摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.

3. 发明授权

US07813183B2 Program and erase methods for nonvolatile memory 有权
标题翻译：非易失性存储器的编程和擦除方法
公开(公告)号：US07813183B2
公开(公告)日：2010-10-12
申请号：US12119060
申请日：2008-05-12
申请人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
发明人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/3404
摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.
摘要翻译：编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲，软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。

4. 发明授权

US08638611B2 Vertical nonvolatile memory devices and methods of operating same 有权
标题翻译：垂直非易失性存储器件及其操作方法
公开(公告)号：US08638611B2
公开(公告)日：2014-01-28
申请号：US13342361
申请日：2012-01-03
申请人： Jaesung Sim , Jungdal Choi
发明人： Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/14 , G11C16/3418
摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).
摘要翻译：集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

5. 发明申请

US20140140140A1 Vertical Nonvolatile Memory Devices and Methods of Operating Same 有权
标题翻译：垂直非易失性存储器件和操作方法相同
公开(公告)号：US20140140140A1
公开(公告)日：2014-05-22
申请号：US14164586
申请日：2014-01-27
申请人： Jaesung Sim , Jungdal Choi
发明人： Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/14 , G11C16/3418
摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).
摘要翻译：集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

6. 发明申请

US20120170375A1 Vertical Nonvolatile Memory Devices and Methods of Operating Same 有权
标题翻译：垂直非易失性存储器件和操作方法相同
公开(公告)号：US20120170375A1
公开(公告)日：2012-07-05
申请号：US13342361
申请日：2012-01-03
申请人： Jaesung Sim , Jungdal Choi
发明人： Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/14 , G11C16/3418
摘要： Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).
摘要翻译：集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

7. 发明申请

US20170215506A1 HAIR EXTENSION CAP AND SYSTEM 审中-公开
公开(公告)号：US20170215506A1
公开(公告)日：2017-08-03
申请号：US15008648
申请日：2016-01-28
申请人： Jaesung Sim
发明人： Jaesung Sim
IPC分类号： A41G5/00 , A41G3/00
CPC分类号： A41G5/0073 , A41G3/0041 , A41G3/0066
摘要： A concave hair extension cap made from spandex, lycra or similar manmade material is provided for attachment to the crown of a user head. The cap has various connection devices integrally attached in a regular arrangement about the surface of the cap or to spaces disposed within the surface of the cap for attachment of the periphery of the connection devices to the borders of the space disposed within the surface of the cap. The arrangement of the connection devices are arrayed in a staggered or symmetrical array. A hair extension having a corresponding connection device is brought into proximity to the hair cap and attached to the connection device in the cap thereby providing extension of hair.

8. 发明申请

US20130215679A1 NONVOLATILE MEMORY DEVICE AND A METHOD OF ADJUSTING A THRESHOLD VOLTAGE OF A GROUND SELECTION TRANSISTOR THEREOF 有权
标题翻译：非易失性存储器件和调整其地电选择晶体管的阈值电压的方法
公开(公告)号：US20130215679A1
公开(公告)日：2013-08-22
申请号：US13772868
申请日：2013-02-21
申请人： Ae-Jeong Lee , Bongyong Lee , Dongchan Kim , Jaesung Sim
发明人： Ae-Jeong Lee , Bongyong Lee , Dongchan Kim , Jaesung Sim
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3409 , H01L27/1157 , H01L27/11582
摘要： A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.
摘要翻译：一种在非易失性存储器件中调整接地选择晶体管的阈值电压的方法包括：在读取操作中向第一接地选择晶体管的栅极提供第一电压，并向第二接地选择晶体管的栅极提供第二电压，读操作。非易失性存储器件包括至少一个串，串具有串选择晶体管，存储单元以及串联连接并堆叠在基板上的第一和第二接地选择晶体管。

9. 发明授权

US11089829B2 Open-top hair cap with fasteners for hair extension 有权
公开(公告)号：US11089829B2
公开(公告)日：2021-08-17
申请号：US16287360
申请日：2019-02-27
申请人： Jaesung Sim
发明人： Jaesung Sim
IPC分类号： A41G5/00
摘要： A head covering with a band portion in a shape of a flat strip or loop and a plurality of flat members that are connected to or a part of the band is disclosed. The flat members projects toward a top side of the band. An outer surface of the flat members includes or is made of a material that can be fastened to a certain corresponding type of material. Thereby, the invention provides a foundation for hairpieces having a fastening component that corresponds to a fastening component used in the invention. The flat members as a whole generally cover a scalp of a head but not completely, exposing the scalp through gaps between flat members. Especially, a top portion or a crown of a scalp is generally exposed due to an open-top construction of the head covering. However, as a single hairpiece is fastened to multiple flat members, the hairpiece in turn works to hold the multiple flat members together. When more hairpieces are attached to flat members, the flat members become structurally solid in a shape that conforms to the contour of the scalp. In so doing, hairpieces cover and bridge the gaps between flat members, thereby completely covering a head.

10. 发明授权

US07821834B2 Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays 有权
标题翻译：利用虚拟存储器单元提高电荷陷阱存储器阵列中的数据可靠性的非易失性存储器件
公开(公告)号：US07821834B2
公开(公告)日：2010-10-26
申请号：US12164533
申请日：2008-06-30
申请人： Jongsun Sel , Yoocheol Shin , Jaesung Sim
发明人： Jongsun Sel , Yoocheol Shin , Jaesung Sim
IPC分类号： G11C16/04
CPC分类号： H01L27/11568 , G11C16/3468 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to be retrieved during read operations and a plurality of immediately adjacent non-addressable “dummy” memory cells configured to store dummy data that is not retrievable during the read operations. The plurality of dummy memory cells include at least one auxiliary dummy memory cell that operates as a buffer against lateral hole transfer within a charge trap layer of the array.
摘要翻译：电荷陷阱闪存器件包括具有电耦合到第一字线的至少第一页电荷陷阱存储单元的闪存阵列。电荷陷阱存储器单元的第一页包括多个可寻址存储器单元，其被配置为存储在读取操作期间要检索的数据，以及多个紧邻的不可寻址的“虚拟”存储单元，其被配置为存储在该期间不可检索的伪数据阅读操作。多个虚拟存储单元包括至少一个辅助虚拟存储单元，其作为抵抗阵列的电荷陷阱层内的侧向空穴传输的缓冲器而起作用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式