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1. 发明授权

US07313738B2 System and method for system-on-chip interconnect verification 失效
标题翻译：系统级芯片互连验证的系统和方法
公开(公告)号：US07313738B2
公开(公告)日：2007-12-25
申请号：US10906388
申请日：2005-02-17
申请人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
IPC分类号： G01R31/28
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

2. 发明申请

US20080215945A1 System and method for system-on-chip interconnect verification 有权
标题翻译：系统级芯片互连验证的系统和方法
公开(公告)号：US20080215945A1
公开(公告)日：2008-09-04
申请号：US11819748
申请日：2007-06-28
申请人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
IPC分类号： G01R31/3177 , G06F13/00 , G06F11/25
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

3. 发明授权

US07865789B2 System and method for system-on-chip interconnect verification 有权
标题翻译：系统级芯片互连验证的系统和方法
公开(公告)号：US07865789B2
公开(公告)日：2011-01-04
申请号：US11819748
申请日：2007-06-28
申请人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
发明人： Serafino Bueti , Adam Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
IPC分类号： G01R31/28
CPC分类号： G06F11/261 , G01R31/31717 , G01R31/318513 , G06F11/2236 , G06F17/5022
摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
摘要翻译：一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较线性反馈移位寄存器和报告错误比较。

4. 发明授权

US07275011B2 Method and apparatus for monitoring integrated circuit temperature through deterministic path delays 失效
标题翻译：通过确定性路径延迟监测集成电路温度的方法和装置
公开(公告)号：US07275011B2
公开(公告)日：2007-09-25
申请号：US11160601
申请日：2005-06-30
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Jason M. Norman , Stanley B. Stanski , Scott T. Vento
IPC分类号： G01K7/01
CPC分类号： G01K3/14 , G01K3/10
摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.
摘要翻译：用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。

5. 发明授权

US07308668B2 Apparatus and method for implementing an integrated circuit IP core library architecture 有权
标题翻译：用于实现集成电路IP核心库架构的装置和方法
公开(公告)号：US07308668B2
公开(公告)日：2007-12-11
申请号：US11160609
申请日：2005-06-30
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Stanley B. Stanski
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Gregory J. Mann , Stanley B. Stanski
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a communication structure included within the library.
摘要翻译：集成电路（IC）架构包括被配置为提供多个单独电路功能的知识产权（IP）核心库。所述IP核以与所述IP核中的各个IP核的定制功能选择相兼容的方式布置，其中通过包括在所述库内的通信结构来访问单独选择的核。

6. 发明授权

US07129821B2 Communication systems and methods using microelectronics power distribution network 失效
标题翻译：通信系统和方法采用微电子配电网络
公开(公告)号：US07129821B2
公开(公告)日：2006-10-31
申请号：US10711082
申请日：2004-08-20
申请人： Serafino Bueti , Adam J. Courchesne , Kai D. Feng , Kenneth J. Goodnow , Gregory J. Mann , Scott T. Vento
发明人： Serafino Bueti , Adam J. Courchesne , Kai D. Feng , Kenneth J. Goodnow , Gregory J. Mann , Scott T. Vento
IPC分类号： G05B11/01
CPC分类号： H04B3/54 , H04B2203/5416
摘要： A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.
摘要翻译：一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。还提供了一种通过微电子芯片的配电网传送通信信号的方法。

7. 发明申请

US20090132732A1 UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路SOC环境通用外围处理器系统
公开(公告)号：US20090132732A1
公开(公告)日：2009-05-21
申请号：US11942000
申请日：2007-11-19
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.
摘要翻译：集成电路（IC）上的通用外围处理器架构包括耦合到接口逻辑器件的第一和第二数据总线，用于实现第一和第二数据总线之间的通信，包括多个信令协议的启用接口。一个或多个处理器与第一和第二数据总线通信以管理IC上的控制功能。数据路径能够在第一和第二数据总线之间传送数据，并与数据存储设备进行通信。数据控制路径实现数据存储设备和处理器之间的通信。

8. 发明申请

US20090132747A1 STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路中SOC环境的通用外围处理器系统结构
公开(公告)号：US20090132747A1
公开(公告)日：2009-05-21
申请号：US12122289
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Jason M. Norman , Clarence R. Ogilvie , Peter A. Sandon , Charles S. Woodruff
IPC分类号： G06F13/14
CPC分类号： G06F13/4059 , G06F2213/0038
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括耦合到接口逻辑器件的第一和第二数据总线，用于实现第一和第二数据总线之间的通信，包括多个信令协议的启用接口。一个或多个处理器与第一和第二数据总线通信以管理IC上的控制功能。数据路径能够在第一和第二数据总线之间传送数据，并与数据存储设备进行通信。数据控制路径实现数据存储设备和处理器之间的通信。

9. 发明授权

US07519941B2 Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry 失效
标题翻译：使用用于选定的电路块的预制和预合格曝光掩模来制造集成电路的方法
公开(公告)号：US07519941B2
公开(公告)日：2009-04-14
申请号：US11279666
申请日：2006-04-13
申请人： Serafino Bueti , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman
发明人： Serafino Bueti , Kenneth J. Goodnow , Gregory J. Mann , Jason M. Norman
IPC分类号： G07F17/50
CPC分类号： G03F1/84
摘要： Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.
摘要翻译：公开了一种制造方法的实施例，其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。该方法的实施例使用多个掩模的步进曝光，包括从该库选择的至少一个掩模，以将芯片设计图案化到硅晶片上，其中芯片设计由两个或更多个互连的电路块组成。因此，对于给定的集成电路设计，可以从库中选择预制/预先限定的掩模，以对设计的一个，一些或所有电路块进行图案化。可选地，附加掩模可以被特别地制造并且被限定以在设计中对其他电路块（例如，应用专用逻辑）进行图案化。以这种方式图案化的电路块可通过通用或定制界面电连接，以完成芯片设计。

10. 发明申请

US20090044054A1 DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS 有权
标题翻译： DIGITAL LOGIC CIRCUIT PATHS的动态关键路径探测器
公开(公告)号：US20090044054A1
公开(公告)日：2009-02-12
申请号：US11834110
申请日：2007-08-06
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G01R31/28
CPC分类号： G06F17/5031 , G01R31/3187 , G06F11/1608 , G06F11/1695 , G06F2217/84
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状态，以及执行预定的校正衡量关键路径。

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