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1. 发明申请

US20060081905A1 Dielectric multilayer of microelectronic device and method of fabricating the same 审中-公开
标题翻译：微电子器件的介质多层及其制造方法
公开(公告)号：US20060081905A1
公开(公告)日：2006-04-20
申请号：US11233335
申请日：2005-09-22
申请人： Seok-jun Won , Dae-jin Kwon , Jong-ho Lee
发明人： Seok-jun Won , Dae-jin Kwon , Jong-ho Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/022 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L29/40114 , H01L29/517 , H01L29/78
摘要： A dielectric multilayer suitable for improving a performance of a microelectronic device and a method of fabricating the dielectric multilayer are provided. The dielectric multilayer of the microelectronic device comprises a composite layer which is formed of oxides of two or more different elements and in which a laminar structure is not formed, and a single layer which is formed on at least one surface of the composite layer and is formed of an oxide of a single element.
摘要翻译：提供一种适用于改善微电子器件的性能的电介质多层及其制造方法。微电子器件的电介质多层包括由两个或更多个不同元素的氧化物形成并且其中没有形成层状结构的复合层和形成在复合层的至少一个表面上的单层，并且是由单一元素的氧化物形成。

2. 发明授权

US07407897B2 Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same 有权
标题翻译：具有多层电介质膜的模拟半导体器件的电容器及其制造方法
公开(公告)号：US07407897B2
公开(公告)日：2008-08-05
申请号：US11173624
申请日：2005-07-01
申请人： Seok-jun Won , Yong-kuk Jeong , Dae-jin Kwon , Min-woo Song , Weon-hong Kim
发明人： Seok-jun Won , Yong-kuk Jeong , Dae-jin Kwon , Min-woo Song , Weon-hong Kim
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L28/65 , Y10S438/957
摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.
摘要翻译：在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。为了获得这些优点，在下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。下电介质膜和上电介质膜可以由SiO 2组成。中间电介质膜可以由HFO 2 N 2构成。

3. 发明申请

US20070169697A1 Method of manufacturing capacitor of semiconductor device by simplifying process of forming dielectric layer and apparatus thereof 审中-公开
标题翻译：通过简化形成介质层的工艺制造半导体器件的电容器的方法及其装置
公开(公告)号：US20070169697A1
公开(公告)日：2007-07-26
申请号：US11710099
申请日：2007-02-23
申请人： Yong-kuk Jeong , Myong-geun Yoon , Seok-jun Won , Dae-jin Kwon
发明人： Yong-kuk Jeong , Myong-geun Yoon , Seok-jun Won , Dae-jin Kwon
IPC分类号： C23C16/00
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/02183 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/02337 , H01L21/3141 , H01L21/31637 , H01L27/10817 , H01L28/40 , H01L28/56 , H01L28/90
摘要： In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.
摘要翻译：在制造半导体器件的电容器及其装置的方法中，仅使用不含反应气体的源气体来沉积电介质层，并且一次执行固化过程。因此，实现了过程简化，产量提高和设备简化。在独立存储器或嵌入式存储器中，步进覆盖得到增强，并且防止了存储节点接触插头的氧化。此外，在使用比独立电容器或嵌入式电容器更厚的电介质层的模拟电容器，RF电容器或高压电容器中，制造工艺被大大简化。

4. 发明授权

US07199003B2 Method of manufacturing capacitor of semiconductor device by simplifying process of forming dielectric layer and apparatus therefor 有权
标题翻译：通过简化形成介质层的工艺来制造半导体器件的电容器的方法及其装置
公开(公告)号：US07199003B2
公开(公告)日：2007-04-03
申请号：US10696465
申请日：2003-10-29
申请人： Yong-kuk Jeong , Myong-geun Yoon , Seok-jun Won , Dae-jin Kwon
发明人： Yong-kuk Jeong , Myong-geun Yoon , Seok-jun Won , Dae-jin Kwon
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/02183 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/02337 , H01L21/3141 , H01L21/31637 , H01L27/10817 , H01L28/40 , H01L28/56 , H01L28/90
摘要： In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.
摘要翻译：在制造半导体器件的电容器及其装置的方法中，仅使用不含反应气体的源气体来沉积电介质层，并且一次执行固化过程。因此，实现了过程简化，产量提高和设备简化。在独立存储器或嵌入式存储器中，步进覆盖得到增强，并且防止了存储节点接触插头的氧化。此外，在使用比独立电容器或嵌入式电容器更厚的电介质层的模拟电容器，RF电容器或高压电容器中，制造工艺被大大简化。

5. 发明申请

US20060017136A1 Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same 有权
标题翻译：具有多层电介质膜的模拟半导体器件的电容器及其制造方法
公开(公告)号：US20060017136A1
公开(公告)日：2006-01-26
申请号：US11173624
申请日：2005-07-01
申请人： Seok-jun Won , Yong-kuk Jeong , Dae-jin Kwon , Min-woo Song , Weon-hong Kim
发明人： Seok-jun Won , Yong-kuk Jeong , Dae-jin Kwon , Min-woo Song , Weon-hong Kim
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L28/65 , Y10S438/957
摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.
摘要翻译：在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。为了获得这些优点，在下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。下电介质膜和上电介质膜可以由SiO 2组成。中间电介质膜可以由HFO 2 N 2构成。

6. 发明授权

US07554146B2 Metal-insulator-metal capacitor and method of fabricating the same 失效
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US07554146B2
公开(公告)日：2009-06-30
申请号：US11317859
申请日：2005-12-23
申请人： Seok-jun Won , Dae-jin Kwon
发明人： Seok-jun Won , Dae-jin Kwon
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/76895 , H01L28/75
摘要： In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first upper electrode pattern on the dielectric layer; an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface; a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern; a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer; and an upper interconnect on the interlayer insulating layer and contacts the second upper electrode.
摘要翻译：在金属绝缘体金属（MIM）电容器和制造MIM电容器的方法中，金属 - 绝缘体 - 金属（MIM）电容器包括：下电极图案，其形成在基板上并且包括具有一部分的导电层作为下互连; 下电极图案上的电介质层; 电介质层上的第一上电极图案; 覆盖第一上电极图案，电介质层和下电极图案并具有平坦化的上表面的层间绝缘层; 形成在所述层间绝缘层中以暴露所述第一上电极图案的第二上电极开口图案; 填充所述开口图案并具有与所述层间绝缘层的上表面基本平齐的上表面的第二上电极; 以及层间绝缘层上的上互连，并与第二上电极接触。

7. 发明申请

US20060163640A1 Method of fabricating metal-insulator-metal capacitor and metal-insulator-metal capacitor manufactured by the method 有权
标题翻译：通过该方法制造金属 - 绝缘体 - 金属电容器和金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US20060163640A1
公开(公告)日：2006-07-27
申请号：US11339151
申请日：2006-01-25
申请人： Jung-min Park , Seok-jun Won , Min-woo Song , Yong-kuk Jeong , Dae-jin Kwon , Weon-hong Kim
发明人： Jung-min Park , Seok-jun Won , Min-woo Song , Yong-kuk Jeong , Dae-jin Kwon , Weon-hong Kim
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.
摘要翻译：在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案，层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。

8. 发明申请

US20060157766A1 Metal-insulator-metal capacitor and method of fabricating the same 失效
公开(公告)号：US20060157766A1
公开(公告)日：2006-07-20
申请号：US11317859
申请日：2005-12-23
申请人： Seok-jun Won , Dae-jin Kwon
发明人： Seok-jun Won , Dae-jin Kwon
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/76895 , H01L28/75
摘要： In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first upper electrode pattern on the dielectric layer; an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface; a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern; a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer; and an upper interconnect on the interlayer insulating layer and contacts the second upper electrode.

9. 发明申请

US20060022245A1 Analog capacitor and method of manufacturing the same 有权
标题翻译：模拟电容及其制造方法
公开(公告)号：US20060022245A1
公开(公告)日：2006-02-02
申请号：US11187489
申请日：2005-07-22
申请人： Yong-kuk Jeong , Seok-jun Won , Dae-jin Kwon , Min-woo Song , Weon-hong Kim
发明人： Yong-kuk Jeong , Seok-jun Won , Dae-jin Kwon , Min-woo Song , Weon-hong Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/022 , H01L21/02172 , H01L21/02274 , H01L21/0228 , H01L21/3143 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/0805 , H01L28/56
摘要： An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.
摘要翻译：提供了能够减小施加电压对电容的影响的模拟电容器和制造模拟电容器的方法。模拟电容器包括形成在基板上的下电极，包括至少一个氧化物层和至少一个氧氮化物层的多层电介质层，所述至少一个氧氮化物层由选自Hf，Al，Zr La，Ba，Sr，Ti，Pb，Bi及其组合形成在下电极上，形成在多层电介质层上的上电极。

10. 发明申请

US20060158829A1 Multi-layered dielectric film of microelectronic device and method of manufacturing the same 有权
公开(公告)号：US20060158829A1
公开(公告)日：2006-07-20
申请号：US11335411
申请日：2006-01-19
申请人： Dae-jin Kwon , Seok-jun Won , Weon-hong Kim , Yong-kuk Jeong , Min-woo Song , Jung-min Park
发明人： Dae-jin Kwon , Seok-jun Won , Weon-hong Kim , Yong-kuk Jeong , Min-woo Song , Jung-min Park
IPC分类号： H01G4/20
CPC分类号： H01G4/10 , H01G4/20
摘要： Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

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