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1. 发明申请

US20080076071A1 Method of forming a fine pattern 审中-公开
标题翻译：形成精细图案的方法
公开(公告)号：US20080076071A1
公开(公告)日：2008-03-27
申请号：US11588496
申请日：2006-10-28
申请人： Seok-Hyun Lim , Chang-Jin Kang , Gyung-Jin Min , Seung-Pil Chung , Dong-Seok Lee
发明人： Seok-Hyun Lim , Chang-Jin Kang , Gyung-Jin Min , Seung-Pil Chung , Dong-Seok Lee
IPC分类号： G03F7/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： First, second and third layers are formed on a substrate for forming a fine pattern. A first mask pattern having a first space is formed on the third layer. A third layer pattern having a second space exposing the second layer is formed. A first sacrificial layer is formed on the second layer having the third layer pattern. A fourth layer is formed on the first sacrificial layer. A double mask pattern including the first and second mask patterns is formed using the second mask pattern in the second space. A second sacrificial layer is formed on the first sacrificial layer. A sacrificial layer pattern having a third space is formed by removing the double mask pattern, the third layer pattern, and a portion of the first sacrificial layer. An insulation layer pattern is formed by removing a portion of the first and second layers.
摘要翻译：首先，在用于形成精细图案的基板上形成第二和第三层。具有第一空间的第一掩模图案形成在第三层上。形成具有暴露第二层的第二空间的第三层图案。在具有第三层图案的第二层上形成第一牺牲层。在第一牺牲层上形成第四层。使用第二空间中的第二掩模图案形成包括第一和第二掩模图案的双掩模图案。在第一牺牲层上形成第二牺牲层。通过去除双掩模图案，第三层图案和第一牺牲层的一部分来形成具有第三空间的牺牲层图案。通过去除第一层和第二层的一部分来形成绝缘层图案。

2. 发明申请

US20070020780A1 Method of processing semiconductor substrate responsive to a state of chamber contamination 审中-公开
标题翻译：响应室污染状态处理半导体衬底的方法
公开(公告)号：US20070020780A1
公开(公告)日：2007-01-25
申请号：US11370478
申请日：2006-03-07
申请人： Kye-Hyun Baek , Chang-Jin Kang , Gyung-Jin Min , Yong-Jin Kim
发明人： Kye-Hyun Baek , Chang-Jin Kang , Gyung-Jin Min , Yong-Jin Kim
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/00
摘要： In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the process condition. If the change in process condition is outside of predetermined margin, a warning may be generated and the process may be stopped.
摘要翻译：在一个实施例中，处理半导体衬底的方法包括在处理每个半导体衬底之前测量处理室污染的状态。响应于室污染的状态来改变工艺条件以补偿室污染状态对工艺条件的影响。如果处理条件的改变超出预定余量，则可能产生警告并且可以停止处理。

3. 发明授权

US07618899B2 Method of patterning a matrix into a substrate via multiple, line-and-space, sacrificial, hard mask layers 有权
标题翻译：通过多个线，空间，牺牲的硬掩模层将基体图案化成衬底的方法
公开(公告)号：US07618899B2
公开(公告)日：2009-11-17
申请号：US11847223
申请日：2007-08-29
申请人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
发明人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
IPC分类号： H01L21/31 , H01L21/308
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086
摘要： Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.
摘要翻译：公开了制造半导体集成电路器件的方法。制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。根据本发明的方法比常规方法更简单和便宜。

4. 发明授权

US07384843B2 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US07384843B2
公开(公告)日：2008-06-10
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

5. 发明申请

US20060128099A1 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US20060128099A1
公开(公告)日：2006-06-15
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

6. 发明授权

US08530954B2 Non-volatile memory devices including first and second blocking layer patterns 有权
标题翻译：包括第一和第二阻挡层图案的非易失性存储器件
公开(公告)号：US08530954B2
公开(公告)日：2013-09-10
申请号：US12491529
申请日：2009-06-25
申请人： Dong-Hyun Kim , Chang-Jin Kang
发明人： Dong-Hyun Kim , Chang-Jin Kang
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
摘要翻译：非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。栅电极位于第一阻挡层图案上。第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

7. 发明授权

US07763544B2 Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
标题翻译：使用精密层作为牺牲层形成精细图案的方法，以及使用其形成自对准触点的方法
公开(公告)号：US07763544B2
公开(公告)日：2010-07-27
申请号：US12496108
申请日：2009-07-01
申请人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
发明人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

8. 发明授权

US07736970B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US07736970B2
公开(公告)日：2010-06-15
申请号：US11869400
申请日：2007-10-09
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

9. 发明授权

US07566659B2 Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same 有权
标题翻译：使用SiGe层作为牺牲层形成精细图案的半导体器件的方法以及使用其形成自对准触点的方法
公开(公告)号：US07566659B2
公开(公告)日：2009-07-28
申请号：US11157435
申请日：2005-06-21
申请人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
发明人： Keun-Hee Bai , Kyeong-Koo Chi , Chang-Jin Kang , Cheol-Kyu Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/0331 , H01L21/0332 , H01L21/76897
摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.
摘要翻译：提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

10. 发明授权

US07564094B2 Non-volatile memory devices and methods of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07564094B2
公开(公告)日：2009-07-21
申请号：US12004985
申请日：2007-12-21
申请人： Dong-Hyun Kim , Chang-Jin Kang
发明人： Dong-Hyun Kim , Chang-Jin Kang
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282
摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
摘要翻译：非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。栅电极位于第一阻挡层图案上。第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

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