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1. 发明授权

US07618899B2 Method of patterning a matrix into a substrate via multiple, line-and-space, sacrificial, hard mask layers 有权
标题翻译：通过多个线，空间，牺牲的硬掩模层将基体图案化成衬底的方法
公开(公告)号：US07618899B2
公开(公告)日：2009-11-17
申请号：US11847223
申请日：2007-08-29
申请人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
发明人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
IPC分类号： H01L21/31 , H01L21/308
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086
摘要： Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.
摘要翻译：公开了制造半导体集成电路器件的方法。制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。根据本发明的方法比常规方法更简单和便宜。

2. 发明授权

US07384843B2 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US07384843B2
公开(公告)日：2008-06-10
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

3. 发明申请

US20060128099A1 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US20060128099A1
公开(公告)日：2006-06-15
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

4. 发明申请

US20070020565A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070020565A1
公开(公告)日：2007-01-25
申请号：US11429071
申请日：2006-05-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
发明人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
IPC分类号： G03F7/26
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.
摘要翻译：提供制造半导体器件的方法。还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

5. 发明授权

US07540970B2 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07540970B2
公开(公告)日：2009-06-02
申请号：US11429071
申请日：2006-05-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
发明人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
IPC分类号： C03C15/00
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.
摘要翻译：提供制造半导体器件的方法。还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

6. 发明申请

US20080076071A1 Method of forming a fine pattern 审中-公开
标题翻译：形成精细图案的方法
公开(公告)号：US20080076071A1
公开(公告)日：2008-03-27
申请号：US11588496
申请日：2006-10-28
申请人： Seok-Hyun Lim , Chang-Jin Kang , Gyung-Jin Min , Seung-Pil Chung , Dong-Seok Lee
发明人： Seok-Hyun Lim , Chang-Jin Kang , Gyung-Jin Min , Seung-Pil Chung , Dong-Seok Lee
IPC分类号： G03F7/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： First, second and third layers are formed on a substrate for forming a fine pattern. A first mask pattern having a first space is formed on the third layer. A third layer pattern having a second space exposing the second layer is formed. A first sacrificial layer is formed on the second layer having the third layer pattern. A fourth layer is formed on the first sacrificial layer. A double mask pattern including the first and second mask patterns is formed using the second mask pattern in the second space. A second sacrificial layer is formed on the first sacrificial layer. A sacrificial layer pattern having a third space is formed by removing the double mask pattern, the third layer pattern, and a portion of the first sacrificial layer. An insulation layer pattern is formed by removing a portion of the first and second layers.
摘要翻译：首先，在用于形成精细图案的基板上形成第二和第三层。具有第一空间的第一掩模图案形成在第三层上。形成具有暴露第二层的第二空间的第三层图案。在具有第三层图案的第二层上形成第一牺牲层。在第一牺牲层上形成第四层。使用第二空间中的第二掩模图案形成包括第一和第二掩模图案的双掩模图案。在第一牺牲层上形成第二牺牲层。通过去除双掩模图案，第三层图案和第一牺牲层的一部分来形成具有第三空间的牺牲层图案。通过去除第一层和第二层的一部分来形成绝缘层图案。

7. 发明授权

US08258610B2 Integrated circuit devices including a multi-layer structure with a contact extending therethrough 失效
标题翻译：集成电路器件包括具有延伸穿过其中的触点的多层结构
公开(公告)号：US08258610B2
公开(公告)日：2012-09-04
申请号：US13016054
申请日：2011-01-28
申请人： Hong Cho , Seung-Pil Chung , Dong-Seok Lee
发明人： Hong Cho , Seung-Pil Chung , Dong-Seok Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/11526 , H01L21/76816 , H01L21/76898 , H01L21/8221 , H01L23/485 , H01L27/0688 , H01L27/105 , H01L27/11529 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.
摘要翻译：集成电路器件在第一衬底层上具有第一衬底层和第一晶体管。第一层间绝缘膜覆盖第一晶体管。第二基板层位于第一层间绝缘膜上，第二晶体管位于第二基板层上。第二层间绝缘膜覆盖第二晶体管。接触件延伸穿过第二层间绝缘膜，第二基板层和第一层间绝缘膜。该接触件包括一下触头和一接触该下接触件的上表面的上触点，以在其间形成界面。该界面位于不大于第二基底的顶表面的高度的高度处，并且大于第二基底层的底表面的高度。

8. 发明授权

US07897512B2 Methods of forming integrated circuit devices including a multi-layer structure with a contact extending therethrough 失效
标题翻译：形成集成电路器件的方法，包括具有延伸穿过其中的接触的多层结构
公开(公告)号：US07897512B2
公开(公告)日：2011-03-01
申请号：US12132755
申请日：2008-06-04
申请人： Hong Cho , Seung-Pil Chung , Dong-Seok Lee
发明人： Hong Cho , Seung-Pil Chung , Dong-Seok Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/11526 , H01L21/76816 , H01L21/76898 , H01L21/8221 , H01L23/485 , H01L27/0688 , H01L27/105 , H01L27/11529 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.
摘要翻译：集成电路器件在第一衬底层上具有第一衬底层和第一晶体管。第一层间绝缘膜覆盖第一晶体管。第二基板层位于第一层间绝缘膜上，第二晶体管位于第二基板层上。第二层间绝缘膜覆盖第二晶体管。接触件延伸穿过第二层间绝缘膜，第二基板层和第一层间绝缘膜。该接触件包括一下触头和一接触该下接触件的上表面的上触点，以在其间形成界面。该界面位于不大于第二基底的顶表面的高度的高度处，并且大于第二基底层的底表面的高度。

9. 发明授权

US07776644B2 Phase change memory cell and method and system for forming the same 有权
标题翻译：相变存储单元及其形成方法和系统
公开(公告)号：US07776644B2
公开(公告)日：2010-08-17
申请号：US11595727
申请日：2006-11-10
申请人： Hong Cho , Seung-Pil Chung , Young-Jae Kim
发明人： Hong Cho , Seung-Pil Chung , Young-Jae Kim
IPC分类号： H01L21/00
CPC分类号： H01L45/143 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By using the low-reactivity halogen element, change to the composition of the phase change material and formation of undercut and deleterious halogen by-product are avoided.
摘要翻译：为了制造相变存储器单元，沉积相变材料层和第一电极材料层。此外，使用包括低反应性卤素元素如溴或碘的蚀刻剂来对第一电极材料进行图案化以形成第一电极。通过使用低反应性卤素元素，可以避免相变材料的组成变化，形成底切和有害的卤素副产物。

10. 发明授权

US07585718B2 Method of manufacturing a carbon nano-tube transistor 失效
标题翻译：制造碳纳米管晶体管的方法
公开(公告)号：US07585718B2
公开(公告)日：2009-09-08
申请号：US11932994
申请日：2007-10-31
申请人： Hong Cho , Seung-Pil Chung , Hong Sik Yoon , Kyung-Rae Byun
发明人： Hong Cho , Seung-Pil Chung , Hong Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L21/336 , H01L21/335
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.
摘要翻译：在第一导电结构上形成包括第一阻挡层，第一绝缘层和第二阻挡层的多层绝缘结构。在第一导电结构上形成第二导电结构和第二绝缘层。蚀刻第二绝缘层和第二导电结构以形成具有第一半径的第一孔和第二孔。间隔件形成在第一孔和第二孔的侧壁上。使用间隔物作为蚀刻掩模蚀刻第二阻挡层和第一绝缘层，以形成具有小于第一半径的第二半径的第三孔。在第一停止层上形成牺牲填料以填充第三孔。去除间隔物后，去除牺牲填料。第一个停止层被蚀刻。从第一导电结构生长碳纳米管。

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