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1. 发明授权

US5528547A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
公开(公告)号：US5528547A
公开(公告)日：1996-06-18
申请号：US332391
申请日：1994-10-31
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

2. 发明授权

US5293337A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
标题翻译：电可擦除可编程只读存储器，具有电场降低控制器
公开(公告)号：US5293337A
公开(公告)日：1994-03-08
申请号：US683733
申请日：1991-04-11
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.
摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

3. 发明授权

US5402373A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
标题翻译：电可擦除可编程只读存储器，具有电场降低控制器
公开(公告)号：US5402373A
公开(公告)日：1995-03-28
申请号：US201036
申请日：1994-02-24
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.
摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

4. 发明授权

US5179427A Non-volatile semiconductor memory device with voltage stabilizing electrode 失效
标题翻译：具有稳压电极的非易失性半导体存储器件
公开(公告)号：US5179427A
公开(公告)日：1993-01-12
申请号：US869123
申请日：1992-04-15
申请人： Ryozo Nakayama , Riichiro Shirota , Yasuo Itoh , Ryouhei Kirisawa , Hideko Odaira , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Seiichi Aritome , Tetsuo Endoh , Fujio Masuoka
发明人： Ryozo Nakayama , Riichiro Shirota , Yasuo Itoh , Ryouhei Kirisawa , Hideko Odaira , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Seiichi Aritome , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483
摘要： A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.
摘要翻译： NAND单元型EEPROM具有形成在衬底上的并行数据传输线，以及存储单元部分，其包括与位线的某个位线相关联的NAND型单元单元的多个NAND型单元单元。该NAND型单元单元具有预选数量的具有控制栅极的数据存储晶体管和选择晶体管的串联电路。衬底电压稳定层被绝缘地设置在衬底之上并且位于与某一位线相邻的场区中。导电层通过接触部分连接到基板，使得在对NAND型单元单元进行写入和擦除模式期间，基板电压可以恒定地设定为固定值的预选电压电位。

5. 发明授权

US5978265A Non-volatile semiconductor memory device with nand type memory cell arrays 失效
标题翻译：具有n型存储单元阵列的非易失性半导体存储器件
公开(公告)号：US5978265A
公开(公告)日：1999-11-02
申请号：US746176
申请日：1991-08-15
申请人： Ryouhei Kirisawa , Riichiro Shirota , Ryozo Nakayama , Seiichi Aritome , Masaki Momodomi , Yasuo Itoh , Fujio Masuoka
发明人： Ryouhei Kirisawa , Riichiro Shirota , Ryozo Nakayama , Seiichi Aritome , Masaki Momodomi , Yasuo Itoh , Fujio Masuoka
IPC分类号： G11C17/12 , G11C16/04 , G11C16/10 , G11C17/00 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.
摘要翻译：公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。并行字线分别连接到存储单元晶体管的控制栅极。在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。因此，逻辑数据被写入所选择的存储单元晶体管中。通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。

6. 发明授权

US5397723A Process for forming arrayed field effect transistors highly integrated on substrate 失效
标题翻译：用于形成高度集成在衬底上的阵列场效应晶体管的工艺
公开(公告)号：US5397723A
公开(公告)日：1995-03-14
申请号：US728585
申请日：1991-07-11
申请人： Riichiro Shirota , Masaki Momodomi , Ryozo Nakayama , Seiichi Aritome , Ryouhei Kirisawa , Tetsuro Endoh , Shigeyoshi Watanabe
发明人： Riichiro Shirota , Masaki Momodomi , Ryozo Nakayama , Seiichi Aritome , Ryouhei Kirisawa , Tetsuro Endoh , Shigeyoshi Watanabe
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265 , H01L21/465
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11517
摘要： A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.
摘要翻译：用于形成用作NAND单元型EEPROM的存储单元的FATMOS晶体管阵列的工艺。多层结构设置在具有由中间绝缘层绝缘的两个层叠导电层的基板上，第一或内部导电层由与基板隔开的第一绝缘层，第二或外部导电层被第二绝缘层。蚀刻第二绝缘层以限定蚀刻层部分的第一阵列。沉积和蚀刻光致抗蚀剂层以限定层部分的第二阵列，每个层部分位于层部分的第一阵列中的两个相邻的层部分之间。用第一和第二层部分作为掩模蚀刻多层结构，从而在衬底上形成多对绝缘栅电极的阵列。将所选择的杂质掺杂到衬底中，其中绝缘栅电极用作掩模，从而在衬底中形成杂质掺杂区域。

7. 发明授权

US5050125A Electrically erasable programmable read-only memory with NAND cellstructure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：US5050125A
公开(公告)日：1991-09-17
申请号：US272404
申请日：1988-11-17
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V）字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

8. 发明授权

US5508957A Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
标题翻译：具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通
公开(公告)号：US5508957A
公开(公告)日：1996-04-16
申请号：US312072
申请日：1994-09-26
申请人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/115 , G11C16/06 , H01L29/788
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/10 , G11C16/16 , H01L27/115
摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管晶体管和地。每个单元晶体管具有浮置栅极和控制栅极。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元。用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

9. 发明授权

US5440509A Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines 失效
标题翻译：电可擦除可编程只读存储器，NAND单元结构和中间电平电压最初应用于位线
公开(公告)号：US5440509A
公开(公告)日：1995-08-08
申请号：US22392
申请日：1993-02-24
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/115
摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V）选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

10. 发明授权

US5321699A Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
标题翻译：具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平
公开(公告)号：US5321699A
公开(公告)日：1994-06-14
申请号：US851286
申请日：1992-03-12
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.
摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。读出放大器连接到位线和比较器。数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

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