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1. 发明授权

US07288845B2 Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits 有权
标题翻译：在集成电路中的底层有源器件，无源器件和/或介电层上制造引线接合焊盘
公开(公告)号：US07288845B2
公开(公告)日：2007-10-30
申请号：US10434524
申请日：2003-05-08
申请人： Sehat Sutardja , Albert Wu , Jin-Yuan Lee , Mou-Shiung Lin
发明人： Sehat Sutardja , Albert Wu , Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/85399 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/04953 , H01L2924/00
摘要： A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.
摘要翻译：用于集成电路（IC）管芯的导线连接结构包括具有有源器件和/或无源器件的半导体晶片。一个或多个电介质层被布置为与有源和/或无源器件相邻。一个或多个金属互连层布置成与有源和/或无源器件相邻。接触垫布置在最外侧金属互连层中。钝化层布置在最外金属互连层上方，并且包括暴露接触焊盘的至少一个钝化开口。焊接层布置在钝化层和有源和/或无源器件上方，并通过钝化开口连接到接触焊盘。接合焊盘的形成不会损坏有源和/或无源器件。

2. 发明授权

US09142527B2 Method of wire bonding over active area of a semiconductor circuit 有权
公开(公告)号：US09142527B2
公开(公告)日：2015-09-22
申请号：US11926156
申请日：2007-10-29
申请人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号： H01L21/4763 , H01L23/00
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

3. 发明授权

US08503186B2 System-in packages 有权
标题翻译：系统包装
公开(公告)号：US08503186B2
公开(公告)日：2013-08-06
申请号：US12841981
申请日：2010-07-22
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H05K7/02
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/3128 , H01L23/5389 , H01L23/60 , H01L24/16 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/82 , H01L24/94 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0251 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/13099 , H01L2224/16225 , H01L2224/24145 , H01L2224/24225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/013
摘要： System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.
摘要翻译：描述了系统包装或多芯片模块，其可以包括载体上的多层芯片和多层虚拟衬底，多个通孔盲目或完全穿过多层芯片并完全通过多层虚拟衬底，通孔中的多个金属插头以及连接到金属插头的多层芯片之间的多个金属互连。多层芯片可以通过金属插头彼此连接或外部电路或结构，例如母板，球栅阵列（BGA）基板，印刷电路板，金属基板，玻璃基板或陶瓷基板和金属互连。

4. 发明申请

US20120228681A1 IMAGE AND LIGHT SENSOR CHIP PACKAGES 有权
标题翻译：图像和光传感器芯片包
公开(公告)号：US20120228681A1
公开(公告)日：2012-09-13
申请号：US13475820
申请日：2012-05-18
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L27/144
CPC分类号： H01L31/0203 , H01L24/45 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/8592 , H01L2924/01015 , H01L2924/01047 , H01L2924/12042 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/20751 , H01L2924/00012
摘要： An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.
摘要翻译：图像或光传感器芯片封装包括具有非感光区域和由非感光区域包围的感光区域的图像或光传感器芯片。在感光区域中有光传感器，光学或彩色滤光片阵列在光传感器和光学或彩色滤光片阵列上的微透镜之上。在非感光区域中，粘合聚合物层和粘合聚合物层中具有一部分的多个金属结构体。在粘合聚合物层的顶表面上并在微透镜上形成透明基底。图像或光传感器芯片封装还包括引线键合线或与图像或光传感器芯片的金属结构接合的柔性基板。

5. 发明申请

US20120098128A1 CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME 有权
标题翻译：芯片结构及其形成方法
公开(公告)号：US20120098128A1
公开(公告)日：2012-04-26
申请号：US13277142
申请日：2011-10-19
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/48
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76807 , H01L23/5286 , H01L23/5329 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.
摘要翻译：具有金属化结构的芯片和具有在金属化结构的第一和第二接触点上的第一和第二开口的绝缘层，连接第一和第二接触点的第一电路层，包括第一迹线部分，第一和第二通孔部分，所述第一迹线部分和所述第一和第二接触点，所述第一电路层包括铜层和在所述铜层下面和所述第一迹线部分的侧壁处的第一导电层，以及第二电路层，其第二通路部分在其底部，其中所述第二电路层包括另一铜层和位于所述另一铜层下方的第二导电层和所述第二迹线部分的侧壁处的第二导电层，以及第二电介质层，第二电路层。

6. 发明授权

US08119446B2 Integrated chip package structure using metal substrate and method of manufacturing the same 有权
标题翻译：使用金属基板的集成芯片封装结构及其制造方法
公开(公告)号：US08119446B2
公开(公告)日：2012-02-21
申请号：US10055560
申请日：2002-01-22
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L21/00 , H01L21/4763
CPC分类号： H01L24/19 , H01L21/568 , H01L23/3114 , H01L23/36 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15311 , H01L2924/15747 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/82 , H01L2224/83 , H01L2924/00
摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on a metal substrate and forming a thin-film circuit layer on top of the dies and the metal substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
摘要翻译：集成芯片封装结构及其制造方法是通过在金属基板上附着金属模并在金属基板的顶部形成薄膜电路层。其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。此外，多个有源器件和内部电路位于管芯的有效表面上。有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

7. 发明授权

US07985653B2 Semiconductor chip with coil element over passivation layer 有权
标题翻译：半导体芯片具有钝化层上的线圈元件
公开(公告)号：US07985653B2
公开(公告)日：2011-07-26
申请号：US12276419
申请日：2008-11-24
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： H01L21/20 , H01L21/8222 , H01L21/8234 , H01L21/4763 , H01L21/8238
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
摘要翻译：一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

8. 发明授权

US07902067B2 Post passivation interconnection schemes on top of the IC chips 有权
标题翻译：后置钝化互连方案在IC芯片之上
公开(公告)号：US07902067B2
公开(公告)日：2011-03-08
申请号：US11906840
申请日：2007-10-04
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
摘要翻译：提供了一种创建互连线的方法。细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。钝化层沉积在电介质层上，在钝化层的表面上形成厚的第二层电介质。在厚的第二层电介质中产生厚而宽的互连线。也可以消除第一层电介质，在已经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。

9. 发明授权

US07524759B2 Post passivation interconnection schemes on top of IC chip 有权
标题翻译：后钝化互连方案在IC芯片顶部
公开(公告)号：US07524759B2
公开(公告)日：2009-04-28
申请号：US11856083
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
摘要翻译：提供了一种创建互连线的方法。细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。钝化层沉积在电介质层上，在钝化层的表面上形成厚的第二层电介质。在厚的第二层电介质中产生厚而宽的互连线。也可以消除第一层电介质，在已经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。

10. 发明授权

US07521812B2 Method of wire bonding over active area of a semiconductor circuit 有权
标题翻译：在半导体电路的有源区上引线键合的方法
公开(公告)号：US07521812B2
公开(公告)日：2009-04-21
申请号：US11678598
申请日：2007-02-25
申请人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号： H01L23/485 , H01L23/49
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
摘要翻译：提供了一种方法和结构，以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。提供了具有有源和/或无源器件的半导体衬底，其中在有源和/或无源器件上形成互连金属化。提供了形成在互连金属化之上的钝化层，其中在钝化层中形成开口以形成互连金属化的上金属层。柔性金属焊盘形成在钝化层上方，其中柔性金属接合焊盘通过开口连接到上金属层，并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。顺应性金属接合焊盘可以由复合金属结构形成。

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