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1. 发明授权

US09030029B2 Chip package with die and substrate 有权
标题翻译：芯片封装，带芯片和基板
公开(公告)号：US09030029B2
公开(公告)日：2015-05-12
申请号：US10055568
申请日：2002-01-22
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L29/00 , H01L29/40 , H01L23/00 , H01L23/36 , H01L23/498 , H01L23/538 , H01L23/64
CPC分类号： H01L24/97 , H01L23/36 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L23/642 , H01L23/645 , H01L24/19 , H01L2221/68363 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
摘要翻译：集成芯片封装结构及其制造方法是通过在硅基板上附着模具并在芯片和硅基板的顶部上形成薄膜电路层。其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。此外，多个有源器件和内部电路位于管芯的有效表面上。有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

2. 发明授权

US08492870B2 Semiconductor package with interconnect layers 有权
标题翻译：具有互连层的半导体封装
公开(公告)号：US08492870B2
公开(公告)日：2013-07-23
申请号：US13159190
申请日：2011-06-13
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L29/00 , H01L21/00 , H05K7/00
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.
摘要翻译：一种包括玻璃基板的芯片封装件，其中所述玻璃基板中的第一开口垂直穿过所述玻璃基板，半导体芯片，包括所述第一开口中的第一部分和所述玻璃基板上的第二部分的布线结构，其中所述第一部分连接到半导体芯片，其中布线结构包括无源器件，其中布线结构包括铜，以及在玻璃衬底上和布线结构上的电介质层，其中电介质层中的第二开口在触点上方接点位于第二开口的底部。

3. 发明授权

US08384508B2 Method for making high-performance RF integrated circuits 有权
标题翻译：制造高性能RF集成电路的方法
公开(公告)号：US08384508B2
公开(公告)日：2013-02-26
申请号：US13077009
申请日：2011-03-31
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/5227 , H01L28/10 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2924/0002 , H01L2924/12044 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.
摘要翻译：提供了一种新的制造半导体电感器的方法和结构。在本发明的第一实施例中，半导体衬底在无源表面区域中设有划线，并且在被动区域周围设有有源电路。在基板的被动表面上至少形成一个接合垫，该接合垫靠近划线的每侧。沉积一层绝缘层，在该绝缘层上沉积一层电介质，至少一个接合焊盘设置在刻划线两边的电介质层的表面上。在电介质层的表面上的划线的每侧形成至少一个电感器。一层钝化层沉积在电介质层上。通过将钝化层的表面与玻璃面板接合来将衬底附接到玻璃面板。衬底从衬底的背面锯切，与划刻线对准。通过蚀刻去除在划线下面的衬底的被动表面中残留的位置的硅，沿着划线分离玻璃面板。在本发明的第二个实施例中，电感器被形成在沉积在钝化层上的聚合物厚层的表面上。

4. 发明授权

US08368213B2 Low fabrication cost, fine pitch and high reliability solder bump 有权
公开(公告)号：US08368213B2
公开(公告)日：2013-02-05
申请号：US10935451
申请日：2004-09-07
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L23/485
CPC分类号： H01L24/12 , H01L24/02 , H01L24/05 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13007 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2225/06513 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2924/00
摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

5. 再颁专利

USRE43674E1 Post passivation metal scheme for high-performance integrated circuit devices 有权
标题翻译：后钝化金属方案用于高性能集成电路器件
公开(公告)号：USRE43674E1
公开(公告)日：2012-09-18
申请号：US11518595
申请日：2006-09-08
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ming-Ta Lei , Ching-Cheng Huang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.
摘要翻译：在已经被常规钝化层覆盖的IC器件的表面上提供了新的后钝化金属互连方案。本发明的金属方案包括叠加常规的钝化层，厚和宽的金属线与厚的介电层和接合焊盘的组合。本发明的互连系统可以用于将功率，接地，信号和时钟线从接合焊盘分配到设置在IC器件的任何位置的器件的电路，而不引入显着的功率下降。由于低阻抗钝化后互连，不需要或更小的ESD电路，因为任何累积的静电放电将均匀分布在芯片上电路的所有结电容上。后钝化金属方案通过接合焊盘，焊接，TAB接合等连接到外部电路。互连金属方案的顶层使用用于引线键合的复合金属形成，复合金属在体导电金属上形成。扩散金属可以施加在本体金属和复合金属之间，另外在体导电金属之下可能需要一层下阻挡金属（UBM）。

6. 发明授权

US08188603B2 Post passivation interconnection schemes on top of IC chip 有权
标题翻译：后钝化互连方案在IC芯片顶部
公开(公告)号：US08188603B2
公开(公告)日：2012-05-29
申请号：US11856076
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
摘要翻译：提供了一种创建互连线的方法。细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。钝化层沉积在电介质层上，在钝化层的表面上形成厚的第二层电介质。在厚的第二层电介质中产生厚而宽的互连线。也可以消除第一层电介质，在已经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。

7. 发明授权

US08138079B2 Method of wire bonding over active area of a semiconductor circuit 有权
标题翻译：在半导体电路的有源区上引线键合的方法
公开(公告)号：US08138079B2
公开(公告)日：2012-03-20
申请号：US11926154
申请日：2007-10-29
申请人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
摘要翻译：提供了一种方法和结构，以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。提供了具有有源和/或无源器件的半导体衬底，其中在有源和/或无源器件上形成互连金属化。提供了形成在互连金属化之上的钝化层，其中在钝化层中形成开口以形成互连金属化的上金属层。柔性金属焊盘形成在钝化层上方，其中柔性金属接合焊盘通过开口连接到上金属层，并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。顺应性金属接合焊盘可以由复合金属结构形成。

8. 发明申请

US20110309473A1 CHIP PACKAGE WITH DIE AND SUBSTRATE 有权
标题翻译：带芯片和基板的芯片包装
公开(公告)号：US20110309473A1
公开(公告)日：2011-12-22
申请号：US13159190
申请日：2011-06-13
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/498
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/97 , H01L2221/68377 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
摘要翻译：使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

9. 发明授权

US08022552B2 Integrated circuit and method for fabricating the same 有权
标题翻译：集成电路及其制作方法
公开(公告)号：US08022552B2
公开(公告)日：2011-09-20
申请号：US11766805
申请日：2007-06-22
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/3192 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2924/09701 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/04953
摘要： A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride.
摘要翻译：一种用于制造集成电路（IC）芯片的方法，包括在半导体衬底上形成厚度在5μm和27μm之间的金属迹线，并在金属迹线上形成钝化层，其中钝化层包括氮化硅层在氮化硅层上的金属迹线和氧化硅层上，或者在金属迹线上包括一层氮氧化硅层，在氮氧化硅层上包括一层氧化硅。

10. 发明授权

US08021918B2 Integrated circuit chips with fine-line metal and over-passivation metal 有权
标题翻译：集成电路芯片与细线金属和过钝化金属
公开(公告)号：US08021918B2
公开(公告)日：2011-09-20
申请号：US11864935
申请日：2007-09-29
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L23/552 , H01L21/76816 , H01L21/76873 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/73 , H01L27/0251 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05664 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/16145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48664 , H01L2224/48724 , H01L2224/48747 , H01L2224/48764 , H01L2224/48824 , H01L2224/48847 , H01L2224/48864 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/01039 , H01L2924/00 , H01L2224/05552
摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.
摘要翻译：集成电路芯片包括硅衬底，位于所述硅衬底中或之上的第一电路，位于所述硅衬底中或之上的第二电路器件，所述硅衬底上的电介质结构，所述电介质结构中的第一互连结构，第一衬垫通过所述第一互连结构连接到所述电压调节器的所述第一节点，所述电介质结构中的第二互连结构，通过所述第二互连结构连接到所述内部电路的所述第一节点的第二焊盘，所述电介质结构上的钝化层，其中所述钝化层中的多个开口暴露所述第一和第二焊盘，以及在所述钝化层上方以及所述第一和第二焊盘之上的第三互连结构。

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