会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Level-shifter circuit for integrated circuits
    • 用于集成电路的电平移位电路
    • US5157281A
    • 1992-10-20
    • US728928
    • 1991-07-12
    • Giovanni SantinSebastiano D'ArrigoMichael C. Smayling
    • Giovanni SantinSebastiano D'ArrigoMichael C. Smayling
    • G11C17/00G11C16/06H01L27/092H01L27/10H01L27/105
    • H01L27/0928H01L27/105
    • A level-shifter circuit includes a deep N-tank to insulate the N-channel portions of transistors from the substrate. The circuit is formed on a P-type substrate coupled to reference voltage Vss. A first field-effect transistor has first and second N+ doped regions formed in a third isolating P- doped region. The third doped region is formed in a fourth isolating N- doped region, which is formed in the substrate. A second transistor has first and second N+ doped regions formed in the same isolation regions as those of the first transistor. A third field-effect transistor has first and second P+ doped regions formed in an isolating N- region that is formed in the substrate. A fourth field-effect transistor has first and second N+ doped regions formed in the same isolation N- region as that of the third transistor. The gate of the first transistor is coupled to a first input. The first doped region of the first transistor is coupled to the output and the second doped region of the first transistor is coupled to the negative voltage Vn. The third doped region is coupled to the negative voltage Vn and the fourth doped region is coupled to the supply voltage Vdd. The second transistor is connected in feedback configuration to the first transistor. The gate of the third transistor is coupled to the second input. The first doped region of the third transistor is coupled to the output and the second doped region of the third transistor is coupled to the voltage Vp, which is more positive than the supply voltage Vdd. The fifth doped region of the third transistor is also coupled to the voltage Vp. The fourth transistor is connected in feedback configuration to the third transistor.
    • 5. 发明授权
    • Process for making a lateral bipolar transistor in a standard CSAG
process
    • 在标准CSAG工艺中制造横向双极晶体管的工艺
    • US4669177A
    • 1987-06-02
    • US791968
    • 1985-10-28
    • Sebastiano D'ArrigoMichael C. Smayling
    • Sebastiano D'ArrigoMichael C. Smayling
    • H01L29/73H01L21/033H01L21/331H01L21/8249H01L23/532H01L27/06H01L29/735H01L21/20
    • H01L21/033H01L21/8249H01L23/53271H01L29/735H01L2924/0002Y10S148/096
    • A method of forming a lateral bipolar transistor in a semiconductor substrate of a second conductivity type by an MOS or CMOS process which includes growing a thin insulating layer over the substrate and diffusing a tank region of a first type of conductivity into the semiconductor substrate of a polarity opposite to that of the second conductivity type. A strip of polysilicon is deposited around a region between the emitter area and collector area on a face of the substrate over said oxide. Next an emitter region having the form of a band enclosing an undiffused central region within the polysilicon strip and a collector region located outside of the strip are diffused into the tank. The polysilicon prevents diffusion of implanted impurity into the tank region over which is superimposed the polysilicon. An electrically conducting layer is formed over the emitter and a portion of the polysilicon.By using a strip of polysilicon to limit diffusion of the emitter and collector regions and by forming the emitter contact over both the emitter and polysilicon it is possible to achieve a smaller emitter geometry than is otherwise possible.
    • 一种通过MOS或CMOS工艺在第二导电类型的半导体衬底中形成横向双极晶体管的方法,其包括在衬底上生长薄绝缘层并将第一类导电性的区域扩散到半导体衬底中 极性与第二导电类型的极性相反。 围绕在所述氧化物上的衬底的表面上的发射极区域和集电极区域之间的区域周围沉积多晶硅条。 接下来,具有包围多晶硅条带内的未扩散中心区域的带的形式的发射极区域和位于条带外部的收集器区域扩散到槽中。 多晶硅防止注入的杂质扩散到叠加多晶硅的槽区中。 在发射极和多晶硅的一部分上形成导电层。 通过使用多晶硅条来限制发射极和集电极区域的扩散,并且通过在发射极和多晶硅两者上形成发射极接触,可以实现比其它可能的更小的发射极几何形状。