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1. 发明授权

US5504708A Flash EEPROM array with P-tank insulated from substrate by deep N-tank 失效
公开(公告)号：US5504708A
公开(公告)日：1996-04-02
申请号：US369025
申请日：1995-01-05
申请人： Giovanni Santin , Giovanni Naso , Sebastiano D'Arrigo , Michael C. Smayling
发明人： Giovanni Santin , Giovanni Naso , Sebastiano D'Arrigo , Michael C. Smayling
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

2. 发明授权

US4736342A Method of forming a field plate in a high voltage array 失效
标题翻译：在高压阵列中形成场板的方法
公开(公告)号：US4736342A
公开(公告)日：1988-04-05
申请号：US798269
申请日：1985-11-15
申请人： Giuliano Imondi , Michael C. Smayling , Sossio Vergara , Sebastiano D'Arrigo
发明人： Giuliano Imondi , Michael C. Smayling , Sossio Vergara , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34 , G11C8/00
CPC分类号： H01L27/115 , G11C16/0441
摘要： An array of electrically programmable semiconductor memory cells of a type having electrically conducting odd and even row lines, left and right column and ground lines and field oxide regions separating adjacent left and right cells. The array has a field plate over the field oxide region which extends underneath both odd and even row lines. A driver is coupled to the odd and even row lines in order to drive one of them to substantially ground potential while the other is driven high to a cell selection voltage.
摘要翻译：一种具有导电奇数和偶数行线，左右列和接地线的电可编程半导体存储器单元的阵列和分隔相邻的左右单元的场氧化物区域。该阵列在场氧化物区域上具有场板，其延伸在奇数行和偶数行之下。驱动器耦合到奇数行和偶数行，以便驱动它们中的一个基本上接地电位，而另一个被驱动到高电平单元选择电压。

3. 发明授权

US5157281A Level-shifter circuit for integrated circuits 失效
标题翻译：用于集成电路的电平移位电路
公开(公告)号：US5157281A
公开(公告)日：1992-10-20
申请号：US728928
申请日：1991-07-12
申请人： Giovanni Santin , Sebastiano D'Arrigo , Michael C. Smayling
发明人： Giovanni Santin , Sebastiano D'Arrigo , Michael C. Smayling
IPC分类号： G11C17/00 , G11C16/06 , H01L27/092 , H01L27/10 , H01L27/105
CPC分类号： H01L27/0928 , H01L27/105
摘要： A level-shifter circuit includes a deep N-tank to insulate the N-channel portions of transistors from the substrate. The circuit is formed on a P-type substrate coupled to reference voltage Vss. A first field-effect transistor has first and second N+ doped regions formed in a third isolating P- doped region. The third doped region is formed in a fourth isolating N- doped region, which is formed in the substrate. A second transistor has first and second N+ doped regions formed in the same isolation regions as those of the first transistor. A third field-effect transistor has first and second P+ doped regions formed in an isolating N- region that is formed in the substrate. A fourth field-effect transistor has first and second N+ doped regions formed in the same isolation N- region as that of the third transistor. The gate of the first transistor is coupled to a first input. The first doped region of the first transistor is coupled to the output and the second doped region of the first transistor is coupled to the negative voltage Vn. The third doped region is coupled to the negative voltage Vn and the fourth doped region is coupled to the supply voltage Vdd. The second transistor is connected in feedback configuration to the first transistor. The gate of the third transistor is coupled to the second input. The first doped region of the third transistor is coupled to the output and the second doped region of the third transistor is coupled to the voltage Vp, which is more positive than the supply voltage Vdd. The fifth doped region of the third transistor is also coupled to the voltage Vp. The fourth transistor is connected in feedback configuration to the third transistor.

4. 发明授权

US4742492A EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor 失效
标题翻译：具有改进的击穿特性的EEPROM存储单元及其驱动电路
公开(公告)号：US4742492A
公开(公告)日：1988-05-03
申请号：US785309
申请日：1985-09-27
申请人： Michael C. Smayling , Sebastiano D'Arrigo
发明人： Michael C. Smayling , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/12 , G11C16/14 , G11C17/00 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/115 , G11C16/0441 , G11C16/12 , G11C16/14
摘要： Erasable programmable memory cell having a control gate, a row line and bit line is disclosed. Line driving circuitry coupled to the bit line and control gate applies a negative voltage to the bit line during the ERASE mode. The latter voltage is such that the voltage across the control gate, floating gate and drain of the floating gate transistor is sufficiently great to cause charging of the floating gate. The construction of the line driving circuit for applying the various voltages, including the negative erase voltage, to the control gate of the floating gate transistor is also disclosed. The line driving circuit is responsive to a control signal indicating the operating mode of the memory, and further includes blocking transistors so that the V.sub.pp voltage of the write operation is not coupled back to the circuit input which receives the control signal.
摘要翻译：公开了具有控制栅极，行线和位线的可擦除可编程存储单元。耦合到位线和控制栅极的线路驱动电路在ERASE模式期间向位线施加负电压。后一电压使得浮动栅极晶体管的控制栅极，浮置栅极和漏极两端的电压足够大以致使浮置栅极充电。还公开了用于将包括负擦除电压的各种电压施加到浮栅晶体管的控制栅极的线路驱动电路的结构。线路驱动电路响应于指示存储器的操作模式的控制信号，并且还包括阻塞晶体管，使得写入操作的Vpp电压不耦合回接收控制信号的电路输入。

5. 发明授权

US4669177A Process for making a lateral bipolar transistor in a standard CSAG process 失效
标题翻译：在标准CSAG工艺中制造横向双极晶体管的工艺
公开(公告)号：US4669177A
公开(公告)日：1987-06-02
申请号：US791968
申请日：1985-10-28
申请人： Sebastiano D'Arrigo , Michael C. Smayling
发明人： Sebastiano D'Arrigo , Michael C. Smayling
IPC分类号： H01L29/73 , H01L21/033 , H01L21/331 , H01L21/8249 , H01L23/532 , H01L27/06 , H01L29/735 , H01L21/20
CPC分类号： H01L21/033 , H01L21/8249 , H01L23/53271 , H01L29/735 , H01L2924/0002 , Y10S148/096
摘要： A method of forming a lateral bipolar transistor in a semiconductor substrate of a second conductivity type by an MOS or CMOS process which includes growing a thin insulating layer over the substrate and diffusing a tank region of a first type of conductivity into the semiconductor substrate of a polarity opposite to that of the second conductivity type. A strip of polysilicon is deposited around a region between the emitter area and collector area on a face of the substrate over said oxide. Next an emitter region having the form of a band enclosing an undiffused central region within the polysilicon strip and a collector region located outside of the strip are diffused into the tank. The polysilicon prevents diffusion of implanted impurity into the tank region over which is superimposed the polysilicon. An electrically conducting layer is formed over the emitter and a portion of the polysilicon.By using a strip of polysilicon to limit diffusion of the emitter and collector regions and by forming the emitter contact over both the emitter and polysilicon it is possible to achieve a smaller emitter geometry than is otherwise possible.
摘要翻译：一种通过MOS或CMOS工艺在第二导电类型的半导体衬底中形成横向双极晶体管的方法，其包括在衬底上生长薄绝缘层并将第一类导电性的区域扩散到半导体衬底中极性与第二导电类型的极性相反。围绕在所述氧化物上的衬底的表面上的发射极区域和集电极区域之间的区域周围沉积多晶硅条。接下来，具有包围多晶硅条带内的未扩散中心区域的带的形式的发射极区域和位于条带外部的收集器区域扩散到槽中。多晶硅防止注入的杂质扩散到叠加多晶硅的槽区中。在发射极和多晶硅的一部分上形成导电层。通过使用多晶硅条来限制发射极和集电极区域的扩散，并且通过在发射极和多晶硅两者上形成发射极接触，可以实现比其它可能的更小的发射极几何形状。

6. 发明授权

US5411908A Flash EEPROM array with P-tank insulated from substrate by deep N-tank 失效
标题翻译：闪存EEPROM阵列，带有P型槽，通过深N槽与基板绝缘
公开(公告)号：US5411908A
公开(公告)日：1995-05-02
申请号：US890577
申请日：1992-05-28
申请人： Giovanni Santin , Giovanni Naso , Sebastiano D'Arrigo , Michael C. Smayling
发明人： Giovanni Santin , Giovanni Naso , Sebastiano D'Arrigo , Michael C. Smayling
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/70
CPC分类号： H01L27/115 , H01L27/11521
摘要： In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.
摘要翻译：根据本发明的一个实施例，非易失性存储器阵列被封装在P坦克中，并且P坦克封装在深N坦克中，两个坦克将存储器阵列与基板分开，并从另一个电路集成存储电路。深N坦克允许对包含存储器阵列的P坦克施加大约-8V的负电压。应用该负电压允许存储器阵列的单元用具有大约+ 10V的峰值的电压脉冲编程，而不是现有技术存储器阵列的+ 18V峰值。因为诸如字线驱动器电路的外部电路需要以+10V而不是+ 18V驱动字线，所以本发明允许使用更薄的栅极绝缘体和节省空间的更短的尺寸来构造该外部电路。

7. 发明授权

US4939558A EEPROM memory cell and driving circuitry 失效
标题翻译： EEPROM存储单元和驱动电路
公开(公告)号：US4939558A
公开(公告)日：1990-07-03
申请号：US273670
申请日：1988-11-21
申请人： Michael C. Smayling , Sebastiano D'Arrigo
发明人： Michael C. Smayling , Sebastiano D'Arrigo
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/7883
摘要： An electrically eraseable programmable memory device which includes a floating gate, heavily doped source and drain regions in which one side thereof is laterally spaced from the floating gate, and the other side has a lightly doped "reach-through" region between the heavily doped region and the channel that underlies the floating gate. A control gate overlies the floating gate. The oxide thickness between the gate and channel is sufficiently thin such that electron tunneling takes place between the floating gate and the "reach through" region.
摘要翻译：一种电可擦除可编程存储器件，其包括浮置栅极，重掺杂源极和漏极区域，其中一侧与浮置栅极横向间隔开，而另一侧在重掺杂区域之间具有轻掺杂的“到达”区域以及浮动门下方的通道。控制门位于浮动栅极之上。栅极和沟道之间的氧化物厚度足够薄，使得在浮动栅极和“到达”区域之间发生电子隧穿。

8. 发明授权

US4823320A Electrically programmable fuse circuit for an integrated-circuit chip 失效
标题翻译：用于集成电路芯片的电可编程熔丝电路
公开(公告)号：US4823320A
公开(公告)日：1989-04-18
申请号：US860940
申请日：1986-05-08
申请人： Michael C. Smayling , Sebastiano D'Arrigo , Giuliano Imondi , Sossio Vergara
发明人： Michael C. Smayling , Sebastiano D'Arrigo , Giuliano Imondi , Sossio Vergara
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C16/0441 , G11C16/10
摘要： A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of the memory element and providing output signal levels corresponding to the programmed states. A switch is coupled to the read circuit output and switches from an open to a closed position in response to a selected output signal level.
摘要翻译：一种用于集成电路芯片的熔丝电路，其包括非易失性存储器元件，用于存储元件的电路编程器，以及用于检测存储器元件的编程状态并提供与编程状态相对应的输出信号电平的读取电路。开关耦合到读取电路输出，并响应于所选择的输出信号电平从开路切换到闭合位置。

9. 发明授权

US4804637A EEPROM memory cell and driving circuitry 失效
标题翻译： EEPROM存储单元和驱动电路
公开(公告)号：US4804637A
公开(公告)日：1989-02-14
申请号：US64416
申请日：1987-06-18
申请人： Michael C. Smayling , Sebastiano D'Arrigo
发明人： Michael C. Smayling , Sebastiano D'Arrigo
IPC分类号： H01L21/336 , H01L29/788 , H01L21/265 , H01L21/70
CPC分类号： H01L29/66825 , H01L29/7883
摘要： An electrically erasable programmable memory device which includes a floating gate, heavily doped source and drain regions in which one side thereof is laterally spaced from the floating gate, and the other side has a lightly doped "reach-through" region between the heavily doped region and the channel that underlies the floating gate. A control gate overlies the floating gate. The oxide thickness between the gate and channel is sufficiently thin such that electron tunnleing takes place between the floating gate and the "reach through" region.
摘要翻译：一种电可擦除可编程存储器件，其包括浮置栅极，重掺杂源极和漏极区域，其中一侧与浮置栅极横向间隔开，另一侧在重掺杂区域之间具有轻掺杂的“到达”区域以及浮动门下方的通道。控制门位于浮动栅极之上。栅极和沟道之间的氧化物厚度足够薄，使得在浮动栅极和“到达”区域之间发生电子隧道。

10. 发明授权

US09122832B2 Methods for controlling microloading variation in semiconductor wafer layout and fabrication 有权
标题翻译：用于控制半导体晶片布局和制造中的微加载变化的方法
公开(公告)号：US09122832B2
公开(公告)日：2015-09-01
申请号：US12512932
申请日：2009-07-30
申请人： Brian Reed , Michael C. Smayling , Scott T. Becker
发明人： Brian Reed , Michael C. Smayling , Scott T. Becker
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.
摘要翻译：在半导体晶片布局中识别有问题的开放区域。有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并且随后从晶片中移除留下期望的永久结构。

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