专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09170979B2 Converging interconnect node controlling operation related to associated future item in dependence upon data predicted based on current transaction data item passing through 有权
标题翻译：根据所通过的当前交易数据项所预测的数据，汇聚与相关未来项目有关的互连节点控制操作
公开(公告)号：US09170979B2
公开(公告)日：2015-10-27
申请号：US13427943
申请日：2012-03-23
申请人： Sean James Salisbury , Andrew David Tune
发明人： Sean James Salisbury , Andrew David Tune
IPC分类号： G06F15/18 , G06F15/173 , G06F9/46
CPC分类号： G06F15/18 , G06F9/466 , G06F13/4022 , G06F15/173 , G06F15/17306 , G06F15/17312
摘要： An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology.
摘要翻译：集成电路包括一个或多个交易数据源以及通过包括多个互连节点的互连电路连接的一个或多个交易数据目的地。在互连节点内有一个或多个会聚互连节点。会聚互连节点包括预测数据生成电路，用于从会聚互连节点读取交易数据的当前项目的特性，并为将来的交易数据项产生相关联的预测数据，该预测数据将在预定时间返回到会聚互连节点未来。该预测数据被存储在预测数据存储电路中，并且由预测数据评估电路读取，以在将其返回到会聚互连节点时控制对应于该预测数据的未来事务数据的处理。互连电路可以具有分支网络拓扑或基于循环环的拓扑。

2. 发明申请

US20130254145A1 INTEGRATED CIRCUIT CONVERGING INTERCONNECT MODE CONTROL 有权
标题翻译：集成电路整合互连模式控制
公开(公告)号：US20130254145A1
公开(公告)日：2013-09-26
申请号：US13427943
申请日：2012-03-23
申请人： Sean James SALISBURY , Andrew David Tune
发明人： Sean James SALISBURY , Andrew David Tune
IPC分类号： G06F15/18
CPC分类号： G06F15/18 , G06F9/466 , G06F13/4022 , G06F15/173 , G06F15/17306 , G06F15/17312
摘要： An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology.
摘要翻译：集成电路包括一个或多个交易数据源以及通过包括多个互连节点的互连电路连接的一个或多个交易数据目的地。在互连节点内有一个或多个会聚互连节点。会聚互连节点包括预测数据生成电路，用于从会聚互连节点读取交易数据的当前项目的特性，并为将来的交易数据项产生相关联的预测数据，该预测数据将在预定时间返回到会聚互连节点未来。该预测数据被存储在预测数据存储电路中，并且由预测数据评估电路读取，以在将其返回到会聚互连节点时控制对应于该预测数据的未来事务数据的处理。互连电路可以具有分支网络拓扑或基于循环环的拓扑。

3. 发明授权

US09294301B2 Selecting between contending data packets to limit latency differences between sources 有权
标题翻译：在竞争数据包之间进行选择以限制源之间的延迟差异
公开(公告)号：US09294301B2
公开(公告)日：2016-03-22
申请号：US13623171
申请日：2012-09-20
申请人： Andrew David Tune , Sean James Salisbury , Alistair Crone Bruce
发明人： Andrew David Tune , Sean James Salisbury , Alistair Crone Bruce
IPC分类号： H04L12/46 , H04L12/701
CPC分类号： H04L12/46 , H04L45/00
摘要： An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.
摘要翻译：仲裁器被配置为选择从发起者发送的几个竞争数据分组中的一个，所述数据分组包括标识发起者和数据的标识符。仲裁器包括：历史缓冲器，用于存储识别多个最近选择的数据分组的发起者的标识符; 以及选择电路，其被配置为根据竞争数据分组的发起者和历史缓冲器中识别的发起者来选择竞争数据分组中的一个，使得选择的数据分组的概率随着选择的数据分组的数量而增加，因为选择了来自同一启动器的数据包。

4. 发明授权

US08619554B2 Interconnecting initiator devices and recipient devices 有权
标题翻译：互连发起者设备和收件人设备
公开(公告)号：US08619554B2
公开(公告)日：2013-12-31
申请号：US11498985
申请日：2006-08-04
申请人： Andrew David Tune , Robin Hotchkiss
发明人： Andrew David Tune , Robin Hotchkiss
IPC分类号： G01R31/08 , H04L12/56
CPC分类号： H04L45/28 , G06F15/16 , G06F15/17375 , H04L69/14
摘要： An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is operable to provide a data route between said initiator device and said recipient device via said at least two parallel connecting routes and to maintain said data route for the duration of said transaction.
摘要翻译：一种用于数据处理设备的互连块，所述互连块可操作以提供一个或多个启动器设备经由其访问一个或多个接收器设备的数据路由，所述互连块包括：第一和第二部分; 所述第一部分包括用于与所述发起者设备之一进行通信的至少一个启动器端口以及用于与所述接收设备之一通信的至少一个接收端口; 所述第二部分包括用于与至少两个接收装置通信的至少两个接收端口，所述第二部分经由至少两个并行连接路径连接到所述第一部分，所述至少两个接收端口可连接到所述至少两个并联连接路线其中响应于从所述第一部分的所述发起者设备之一接收的请求，以执行与所述第二部分通信的所述至少两个接收者之一的事务，所述互连块可操作以提供所述启动器设备之间的数据路由并且经由所述至少两个并行连接路由表示所述接收方设备，并且在所述事务持续期间保持所述数据路由。

5. 发明授权

US08285912B2 Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure 有权
标题翻译：用于数据处理设备的通信基础设施和这种通信基础设施的操作方法
公开(公告)号：US08285912B2
公开(公告)日：2012-10-09
申请号：US12461345
申请日：2009-08-07
申请人： Brett Stanley Feero , Peter Andrew Riocreux , Andrew David Tune
发明人： Brett Stanley Feero , Peter Andrew Riocreux , Andrew David Tune
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0038
摘要： A communication infrastructure for a data processing apparatus, and a method of operation of such a communication infrastructure are provided. The communication infrastructure provides first and second switching circuits interconnected via a bidirectional link. Both of the switching circuits employ a multi-channel communication protocol, such that for each transaction a communication path is established from an initiating master interface to a target slave interface, with that communication path comprising m channels. The m channels comprise one or more forward channels from the initiating master interface to the target slave interface and one or more reverse channels from the target slave interface to the initiating master interface, and handshaking signals are associated with each of the m channels. The bidirectional link comprises n connection lines, where n is less than m, the bidirectional link supporting a first communication path from the first switching circuit to the second switching circuit and a second communication path in an opposite direction from the second switching circuit to the first switching circuit. Control circuitry is used to multiplex at least one forward channel of the first communication path and at least one reverse channel of the second communication path, with the multiplexing being performed in dependence on the handshaking signals associated with the channels to be multiplexed. This allows the 2m channels formed by the first and second communication paths to be provided by the n connection lines of the bidirectional link.
摘要翻译：提供了一种用于数据处理装置的通信基础设施，以及这种通信基础设施的操作方法。通信基础设施提供通过双向链路互连的第一和第二交换电路。两个开关电路采用多通道通信协议，使得对于每个事务，通信路径从启动主接口建立到目标从接口，该通信路径包括m个信道。 m个信道包括从初始主接口到目标从接口的一个或多个前向信道，以及从目标从接口到发起主接口的一个或多个反向信道，以及握手信号与m个信道中的每一个相关联。双向链路包括n个小于m的n个连接线，支持从第一开关电路到第二开关电路的第一通信路径的双向链路和与第二开关电路相反的第二通信路径开关电路。控制电路用于复用第一通信路径的至少一个前向信道和第二通信路径的至少一个反向信道，根据与要多路复用的信道相关联的握手信号执行复用。这允许由第一和第二通信路径形成的2m信道由双向链路的n个连接线提供。

6. 发明授权

US07664901B2 Data processing apparatus and method for arbitrating access to a shared resource 有权
标题翻译：用于仲裁对共享资源的访问的数据处理装置和方法
公开(公告)号：US07664901B2
公开(公告)日：2010-02-16
申请号：US11727647
申请日：2007-03-27
申请人： Peter Andrew Riocreux , Alistair Crone Bruce , Andrew David Tune
发明人： Peter Andrew Riocreux , Alistair Crone Bruce , Andrew David Tune
IPC分类号： G06F13/38
CPC分类号： G06F13/14 , G06F13/36
摘要： A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group. Responsive to a predetermined event, the arbitration circuitry re-applies the priority ordering operation within at least one priority group prior to a subsequent performance of the priority determination operation. Such an approach has been found to provide a particularly flexible mechanism for performing arbitration, allowing a wide variety of different arbitration schemes to be implemented using the same arbitration hardware.
摘要翻译：数据处理装置和方法正在提供仲裁对共享资源的访问。数据处理装置具有共享对共享资源的访问的多个逻辑元件，以及响应于一个或多个逻辑元件对于共享资源的访问的请求的仲裁电路，以执行优先级确定操作，以选择请求作为获胜请求。仲裁电路应用仲裁策略以将优先级与每个逻辑元件相关联，仲裁策略包括多个优先级组，每个优先级组具有不同的优先级并且包含至少一个逻辑元件。在每个优先级组内，仲裁电路应用优先级排序操作来将相对优先级归因于该优先级组内的逻辑元件。响应于预定事件，仲裁电路在随后执行优先级确定操作之前在至少一个优先级组内重新应用优先级排序操作。已经发现这种方法提供了一种用于执行仲裁的特别灵活的机制，允许使用相同的仲裁硬件来实现各种不同的仲裁方案。

7. 发明申请

US20090210594A1 BUS INTERCONNECT DEVICE AND A DATA PROCESSING APPARATUS INCLUDING SUCH A BUS INTERCONNECT DEVICE 有权
标题翻译：总线互连设备和包括这种总线互连设备的数据处理设备
公开(公告)号：US20090210594A1
公开(公告)日：2009-08-20
申请号：US12309740
申请日：2006-08-04
申请人： Alistair Crone Bruce , Andrew David Tune
发明人： Alistair Crone Bruce , Andrew David Tune
IPC分类号： G06F13/42 , G06F13/14
CPC分类号： H01P3/02
摘要： A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.
摘要翻译：提供一种总线互连装置，其包括用于将多个装置耦合在一起的平行板波导。这提供了用于在数据处理装置内提供互连功能的有效且灵活的方法。

8. 发明授权

US09507737B2 Arbitration circuitry and method 有权
标题翻译：仲裁电路和方法
公开(公告)号：US09507737B2
公开(公告)日：2016-11-29
申请号：US13622427
申请日：2012-09-19
申请人： Arthur Laughton , Andrew David Tune
发明人： Arthur Laughton , Andrew David Tune
IPC分类号： G06F13/14 , G06F13/00 , G06F13/36
CPC分类号： G06F13/14 , G06F13/36 , G06F2213/0038
摘要： Arbitration circuitry is provided to select an output from between multiple inputs each having an associated priority value. A tie-break value is appended to the least significant bits of each of the priority values to form extended priority values before those extended priority values are compared. Thus, if two priority values are equal, then the appended tie-break bits are used to determine which of the two inputs will be selected as having the higher priority.
摘要翻译：提供仲裁电路以从多个输入之间选择输出，每个输入具有相关联的优先级值。在每个优先级值的最低有效位之后追加中断值，以在比较扩展优先级值之前形成扩展优先级值。因此，如果两个优先级值相等，则附加的中断位用于确定两个输入中的哪一个将被选择为具有较高优先级。

9. 发明授权

US07809972B2 Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain 有权
标题翻译：用于在第一时钟域和第二时钟域之间转换信号的数据处理装置和方法
公开(公告)号：US07809972B2
公开(公告)日：2010-10-05
申请号：US11729984
申请日：2007-03-30
申请人： Andrew David Tune , Pierre Michel Broyer
发明人： Andrew David Tune , Pierre Michel Broyer
IPC分类号： G06F1/12 , G01R27/28
CPC分类号： G06F5/06
摘要： A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period.
摘要翻译：数据处理装置包括用于产生在具有第一时钟周期的第一时钟域中操作的信号的第一组件，以及用于接收在具有第二时钟周期的第二时钟域中操作的信号的第二组件。第二个时钟周期与第一个时钟周期同步但比第一个时钟周期慢。提供接口电路，用于在第一时钟域和第二时钟域之间转换信号，接口电路在第一时钟域中工作，并且包括用于临时缓冲由第一分量产生的信号的存储元件，然后将该信号输出到第二时钟域零件。考虑到指定的第一时钟周期表示的第二分量的输入延迟时间的指定输入延迟值，使能电路用于控制来自存储元件的信号的输出。

10. 发明申请

US20080244299A1 Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain 有权
标题翻译：用于在第一时钟域和第二时钟域之间转换信号的数据处理装置和方法
公开(公告)号：US20080244299A1
公开(公告)日：2008-10-02
申请号：US11729984
申请日：2007-03-30
申请人： Andrew David Tune , Pierre Michel Broyer
发明人： Andrew David Tune , Pierre Michel Broyer
IPC分类号： G06F1/12
CPC分类号： G06F5/06
摘要： The present invention provides a data processing apparatus and method for translating a signal between a first clock domain and a second clock domain. The data processing apparatus may comprise a first component for generating a signal, the first component operating in the first clock domain having a first clock period, and a second component for receiving the signal, the second component operating in the second clock domain having a second clock period. In one embodiment, the second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Further, enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period. Hence, such a data processing apparatus controls translation of a signal from a fast clock domain to a slow clock domain where the input delay time of the component in the slower clock domain is configured in terms of the fast clock period, thereby enabling the latency to be tuned having regard to the slow clock domain input delay constraints. In an alternative embodiment, a similar arrangement is used to control translation of a signal from a slow domain to a fast clock domain, with the output delay time of the component in the slow clock domain being configured in terms of the fast clock period.
摘要翻译：本发明提供一种用于在第一时钟域和第二时钟域之间转换信号的数据处理装置和方法。数据处理装置可以包括用于产生信号的第一组件，在具有第一时钟周期的第一时钟域中操作的第一组件和用于接收该信号的第二组件，在第二时钟域中操作的第二组件具有第二组件时钟周期。在一个实施例中，第二时钟周期与第一时钟周期同步但是比第一时钟周期慢。提供接口电路，用于在第一时钟域和第二时钟域之间转换信号，接口电路在第一时钟域中工作，并且包括用于临时缓冲由第一分量产生的信号的存储元件，然后将该信号输出到第二时钟域零件。此外，使能电路用于根据指定的输入延迟值来控制来自存储元件的信号的输出，该输入延迟值用于识别以第一时钟周期表示的第二分量的输入延迟时间。因此，这样的数据处理装置控制从快速时钟域到慢时钟域的信号的转换，其中较慢时钟域中的组件的输入延迟时间是根据快速时钟周期配置的，从而使等待时间考虑到慢时钟域输入延迟约束，需要进行调整。在替代实施例中，类似的布置用于控制从慢域到快时钟域的信号的转换，其中慢时钟域中的组件的输出延迟时间是根据快速时钟周期配置的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式